JPH0348928U - - Google Patents

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Publication number
JPH0348928U
JPH0348928U JP10998189U JP10998189U JPH0348928U JP H0348928 U JPH0348928 U JP H0348928U JP 10998189 U JP10998189 U JP 10998189U JP 10998189 U JP10998189 U JP 10998189U JP H0348928 U JPH0348928 U JP H0348928U
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JP
Japan
Prior art keywords
integrated circuit
output stage
resistor
inverter
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10998189U
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English (en)
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JP2528977Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed filed Critical
Priority to JP1989109981U priority Critical patent/JP2528977Y2/ja
Publication of JPH0348928U publication Critical patent/JPH0348928U/ja
Application granted granted Critical
Publication of JP2528977Y2 publication Critical patent/JP2528977Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】
第１図はこの考案の第１の実施例の半導体集積
回路の回路図、第２図は第２の実施例の回路図、
第３図は第３の実施例の回路図である。第４図は
従来の半導体集積回路の回路図である。 ＩＮＶ１……前段のインバータ、ＩＮＶ２……
出力段のインバータ、Ｍ１〜Ｍ７……ＭＯＳ型ト
ランジスタ、Ｒ１……抵抗、ＯＵＴ……出力端子
。

Claims (1)

  1. 【実用新案登録請求の範囲】 １ 相補型ＭＯＳ集積回路において、 出力段の前段のインバータとグランドライン間
    にＮチヤンネルＭＯＳ型トランジスタを接続する
    とともに、出力段の入力部と電源との間に抵抗を
    接続したことを特徴とする半導体集積回路。 ２ 相補型ＭＯＳ集積回路において、 出力段の前段のインバータと電源間にＰチヤン
    ネルＭＯＳ型トランジスタを接続するとともに、
    出力段の入力部とグランドライン間に抵抗を接続
    したことを特徴とする半導体集積回路。
JP1989109981U 1989-09-19 1989-09-19 半導体集積回路 Expired - Lifetime JP2528977Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989109981U JP2528977Y2 (ja) 1989-09-19 1989-09-19 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989109981U JP2528977Y2 (ja) 1989-09-19 1989-09-19 半導体集積回路

Publications (2)

Publication Number Publication Date
JPH0348928U true JPH0348928U (ja) 1991-05-13
JP2528977Y2 JP2528977Y2 (ja) 1997-03-12

Family

ID=31658539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989109981U Expired - Lifetime JP2528977Y2 (ja) 1989-09-19 1989-09-19 半導体集積回路

Country Status (1)

Country Link
JP (1) JP2528977Y2 (ja)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843626A (ja) * 1981-09-09 1983-03-14 Toshiba Corp 論理回路
JPS59108425A (ja) * 1982-12-13 1984-06-22 Mitsubishi Electric Corp 相補型ｍｏｒ集積回路
JPS61189018A (ja) * 1985-02-18 1986-08-22 Hitachi Ltd 論理素子の誤動作防止回路
JPS63128644A (ja) * 1986-11-18 1988-06-01 Mitsubishi Electric Corp 半導体装置のオプシヨン切換回路
JPS6444618A (en) * 1987-08-13 1989-02-17 Toshiba Corp Reset signal generating circuit
JPH01183216A (ja) * 1988-01-14 1989-07-21 Nec Corp 出力バッファ回路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843626A (ja) * 1981-09-09 1983-03-14 Toshiba Corp 論理回路
JPS59108425A (ja) * 1982-12-13 1984-06-22 Mitsubishi Electric Corp 相補型ｍｏｒ集積回路
JPS61189018A (ja) * 1985-02-18 1986-08-22 Hitachi Ltd 論理素子の誤動作防止回路
JPS63128644A (ja) * 1986-11-18 1988-06-01 Mitsubishi Electric Corp 半導体装置のオプシヨン切換回路
JPS6444618A (en) * 1987-08-13 1989-02-17 Toshiba Corp Reset signal generating circuit
JPH01183216A (ja) * 1988-01-14 1989-07-21 Nec Corp 出力バッファ回路

Also Published As

Publication number Publication date
JP2528977Y2 (ja) 1997-03-12

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term