JPH0348697B2 - - Google Patents

Description

[Detailed description of the invention] [Summary] Digital phase-locked loop circuit (hereinafter referred to as DPLL)
An out-of-synchronization detection means is provided in the
If the DPLL circuit is not continuously locked, the output frequency of the reference frequency generating means can be switched or changed to respond to an input signal with a wide frequency range or an input signal assigned to a predetermined channel. This makes it possible to achieve phase synchronization.

[Industrial Application Field] The present invention relates to a DPLL circuit that can achieve phase synchronization with an input signal in a wide frequency range or with an input signal assigned to a predetermined channel.

[Conventional technology]

In order to widen the lock range of the DPLL circuit,
Conventionally, there have been methods such as increasing the frequency division ratio of the frequency division switching section or increasing the number of stages of the sequential filter, but these methods complicate the specific circuit configuration, and other methods require The DPLL method is known, but this method requires the detection and adjustment of binary frequency signals over a wide range from the upper limit to the lower limit of the lock frequency range, and has drawbacks such as a large steady-state phase error. It was hot.

[Problem that the invention seeks to solve]

The objective is to obtain a DPLL circuit that can be applied to input signals in a wide frequency range or input signals assigned to channels in a wide frequency range.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention, and shows a reference frequency generating means 1, a variable frequency dividing means 2, a phase comparing means 3, and a known DPLL having the phase comparing means 3. The circuit is further provided with out-of-synchronization detection means 4 to which the output of the phase comparison means 3 for comparing the input signal and the output signal is supplied, and when the out-of-synchronization detection means 4 detects out-of-synchronization of the DPLL circuit, The frequency generated by the reference frequency generating means 1 is switched or changed so that the DPLL circuit can lock onto the input signal.

[Effect]

In the present invention, as is clear from the principle diagram in FIG. The first loop consisting of.

A second circuit comprising a phase comparison means 3, an out-of-synchronization detection means 4, a reference frequency generation means 1, a variable frequency division means 2, and a feedback path 5 which returns the output of the frequency division means 2 to the input of the phase comparison means 3. loop.

Two loops are formed.

This first loop is, for example, "How to use PLL-IC" co-authored by Masayasu Hata and Keisuke Furukawa (Sanpo Publishing Co., Ltd.
It operates as a known DPLL circuit as described in pages 139 to 156 (published on April 20, 1983, 7th edition).

The second loop configured according to the present invention is configured to detect the frequency of the input signal when the desynchronization detection means 4 detects that the first loop is continuously unlocked. The first loop is locked to the frequency of the input signal by switching or changing the output frequency of the reference frequency generating means 1 according to the direction of the deviation from the lock range.

To explain with reference to FIG. 2, when the reference frequency from the reference frequency generating means 1 is A and the frequency range that can be locked by the first loop is within the range a centered on the reference frequency A, the input If the frequency of the signal is X outside the range of a, the phase comparison means 3 generates an output indicating the phase difference between the input signal and the feedback signal, and the desynchronization detection means 4 generates an output indicating the phase difference. When it is determined that the output of the means 3 is continuous for a predetermined period of time, the reference frequency from the reference frequency generating means 1 is lowered by one step to the frequency B.
Since the frequency range in which the first loop can be locked is changed to the range b, the first loop is locked to the input signal having the frequency to be output.

If the frequency of the input signal is a frequency Y that is lower than the above-mentioned frequency , the first loop is phase-locked to this frequency Y.

When changing the reference frequency from the reference frequency generating means 1, the reference frequency can be changed continuously, or as shown in FIG.
By setting the frequency intervals of the reference frequencies so that the lockable frequency ranges of the first loop overlap, it is possible to obtain an output that is phase-synchronized with input signals of continuous frequencies.

Furthermore, if _the interval Δf between the reference frequencies is made larger than the frequency range df that can be locked by each reference frequency f ₁ , f ₂ . A phase synchronized output is obtained only for input signals in a frequency range that can be locked. Therefore, if the reference frequency is set to a frequency that can be locked for each predetermined channel, the second loop selects a channel. , the first loop allows phase synchronization for each channel.

It is clear that the interval Δf between the reference frequencies at this time does not need to be constant.

〔Example〕

FIG. 4 shows an embodiment of the DPLL circuit according to the present invention, in which a reference frequency oscillator 11 corresponds to the reference frequency generating means 1 of FIG. 1, a switching frequency divider 12 corresponding to the variable frequency dividing means 2, and a Circulator 13,
Phase comparator 1 also corresponds to phase comparison means 3
4, a known system as described in the above publication, consisting of a sequential filter 15 and a frequency divider 16.
In the DPLL circuit, that is, in the first loop, the first
A lock detection circuit 17 corresponding to the out-of-synchronization detection means 4 shown in the figure and a frequency control circuit 18 for controlling the reference frequency from the reference frequency oscillator 11 are provided, and as explained with reference to FIG. The frequency control circuit 18 may be one that controls the oscillation frequency of the reference frequency oscillator 11, or may be one that selects and outputs signals of a plurality of different frequencies.

This first loop circuit includes a phase comparator 14 that compares the phases of the input pulse and the feedback signal from the frequency divider 16, quantizes the phase lead or lag into +1 or -1, and outputs the quantized result due to noise. A sequential filter 15 for preventing erroneous control, a switching frequency divider 12 whose frequency division ratio is controlled by the output based on the phase error from this sequential filter 15, and a frequency division ratio of this switching frequency divider 12. A known DPLL circuit is constructed of a frequency divider 13 for smoothing and outputting sudden frequency changes caused by switching, and a frequency divider 16 for obtaining a feedback signal.

If the frequency of the signal input to the DPLL circuit is outside the frequency range in which the DPLL circuit can lock, the phase comparator 14 outputs an error signal, and the delay time due to the operation time of the sequential filter 15 increases. The error signal continues to be output even after the elapse of time.

In the present invention, the lock detection circuit 17 measures the time during which the phase comparator 14 continuously outputs this error signal, and when this time exceeds the delay time, the reference frequency oscillator is output via the frequency control circuit 18. The reference frequency from 11 is varied as described above so that this DPLL circuit is locked to the input signal.

FIG. 5 shows another embodiment, in which a first loop is composed of a phase comparator 14, a sequential filter 15, a timing divider 25, a frequency divider 13, and a frequency divider 16, and a variable reference frequency A fixed frequency oscillator 23 and a pulse insertion/removal frequency divider 24 are used to supply the frequency, and a filter 21 and a selector 22 for controlling pulse insertion/removal of the pulse insertion/removal frequency divider 24 are used as means for detecting out-of-synchronization according to the present invention. It was established. Components equivalent to those in the embodiment shown in FIG. 4 are designated by the same reference numerals as in FIG. 4.

Although the first loop of this embodiment is different due to the use of the timing divider 25,
This loop as a whole operates in the same manner as the embodiment shown in FIG.

The filter 21 constituting the out-of-synchronization detection means filters the low frequency component of the error output from the phase detector 14 and supplies it to the selector 22. For example, a low frequency error signal is supplied from this phase detector 14, so an output is generated, and the selector 22 selects the pulse insertion/extraction frequency divider 24 according to the polarity of the error signal.
, thereby substantially changing the frequency of the signal from the reference frequency oscillator 23 applied to the timing divider 25 to phase-lock the first loop to the input signal.

In the embodiment shown in FIG. 5, the input frequency f _o 50kHz oscillation frequency _f o of the fixed frequency oscillator 23
10MHz Number of stages of filter 21 a 4 stages Number of selectors 22 b 3 stages Pulse insertion/extraction division ratio c 400±1/400 Number of stages of sequential filter 15 d
3-stage timing frequency division ratio e 1/3-1/4-1/5 If the output frequency f _{n is} 100kHz, the frequency division ratio A of the frequency divider 13 is 1/25, and the frequency division ratio of the frequency divider 16 is 1 /2, and phase comparator 1
4. The lock range of the loop consisting of the sequential filter 15, timing divider 25, frequency divider 13, and frequency divider 16 is d・T _nax = (n・A・B−1) e ₀・1/f ₀ +e _nax・1/f ₀ , and when we enter the above values, we get 3×T _nax = (3×25×2−1)×4 ×4×1/10 ⁷ ×3×1/10 ⁷ , so The lock range for the input frequency is f _nax = 1/T _nax = 50083.472Hz f _nio = 1/T _nio = 49916.806 Hz, that is, f _nax = 50 kHz + 83.472 Hz f _nio = 50 kHz - 83.194 Hz.

Then, the step width of the pulse insertion/extraction frequency division ratio c is 1
Since each step is 1/400, selector 2
The change in output frequency ∆f when switching 2 by 1 step is as follows: ∆f = f ₀ × 1/400 × e ₀ × A × B = 10 ⁷ × 1/400 × 1/4 × 1/25 × 1/2 = It becomes 125Hz.

Therefore, in order to continuously lock the input frequency, as shown in FIG. 5, the lock frequency range df at one pulse insertion/extraction division ratio c must be made larger than the frequency change Δf caused by the above steps. It is necessary to keep

〔Effect of the invention〕

According to the present invention, it is possible to realize a DPLL circuit that can handle input signals in a wide frequency band, and the DPLL circuit has a sufficiently wide lock range even if the number of sequential filter stages is increased to eliminate negative effects such as noise. is obtained.

Furthermore, by setting the output frequency of the reference frequency oscillator for each center frequency of the channel,
Conventionally, the number of DPLL circuits corresponding to the number of channels was required, but with the present invention, one
A special effect can be achieved in that a DPLL circuit is sufficient.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the principle of the present invention, Figure 2 is a block diagram showing the principle of the present invention.
3 and 3 are diagrams for explaining the operation,
FIG. 4 and FIG. 5 are diagrams showing different embodiments, respectively. 1 is a reference frequency generating means, 2 is a variable frequency dividing means,
3 is a phase comparison means, and 4 is an out-of-synchronization detection means.

Claims (1)

[Scope of Claims] 1. A reference frequency generating means 1 that outputs a reference frequency signal having a predetermined number of pulses in a fixed period, and divides the reference frequency signal at a frequency division ratio according to a control input, and outputs an output signal. A phase that compares the phase of the generated variable frequency dividing means 2 and the fed back output of the variable frequency dividing means and the input signal, and controls the frequency division ratio of the variable frequency dividing means so that the phases of both are synchronized. Comparison method 3
A digital phase synchronization circuit having: a digital phase synchronization circuit further comprising an out-of-synchronization detection means 4 for detecting out-of-synchronization for a predetermined period or more by the phase comparison means and changing the frequency of the reference frequency signal. Wideband digital phase-locked circuit.