JPH0348241U - - Google Patents
Info
- Publication number
- JPH0348241U JPH0348241U JP10990989U JP10990989U JPH0348241U JP H0348241 U JPH0348241 U JP H0348241U JP 10990989 U JP10990989 U JP 10990989U JP 10990989 U JP10990989 U JP 10990989U JP H0348241 U JPH0348241 U JP H0348241U
- Authority
- JP
- Japan
- Prior art keywords
- base
- cavity
- external terminal
- utility
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図、第２図は、本考案の実施例を示し、ａ
図はベースの平面図の一部、ｂ図はその断面図を
示すものである。第３図、第４図は従来のサーデ
イツプパツケージのベースの例を示し、ａ図はベ
ースの平面図の一部、ｂ図はその断面図を示すも
のである。 ここに、１−１〜１−６……外部端子リード、
２……ベース、３……半導体チツプ、４……低融
点ガラス、５……ボンデイングワイヤ、６……キ
ヤビテイ、である。
図はベースの平面図の一部、ｂ図はその断面図を
示すものである。第３図、第４図は従来のサーデ
イツプパツケージのベースの例を示し、ａ図はベ
ースの平面図の一部、ｂ図はその断面図を示すも
のである。 ここに、１−１〜１−６……外部端子リード、
２……ベース、３……半導体チツプ、４……低融
点ガラス、５……ボンデイングワイヤ、６……キ
ヤビテイ、である。
Claims (1)
- サーデイツプパツケージに於ける外部端子リー
ドの一端が、ベースのキヤビテイ内に突出した構
造を有することを特徴とする集積回路パツケージ
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10990989U JPH0348241U (ja) | 1989-09-19 | 1989-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10990989U JPH0348241U (ja) | 1989-09-19 | 1989-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0348241U true JPH0348241U (ja) | 1991-05-08 |
Family
ID=31658468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10990989U Pending JPH0348241U (ja) | 1989-09-19 | 1989-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0348241U (ja) |
-
1989
- 1989-09-19 JP JP10990989U patent/JPH0348241U/ja active Pending