JPH0295246U - - Google Patents

Info

Publication number
JPH0295246U
JPH0295246U JP305589U JP305589U JPH0295246U JP H0295246 U JPH0295246 U JP H0295246U JP 305589 U JP305589 U JP 305589U JP 305589 U JP305589 U JP 305589U JP H0295246 U JPH0295246 U JP H0295246U
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
insulating container
semiconductor
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP305589U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP305589U priority Critical patent/JPH0295246U/ja
Publication of JPH0295246U publication Critical patent/JPH0295246U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Die Bonding (AREA)
  • Semiconductor Memories (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第1図は、本考案の第1の実施例を示すP・P
GA型半導体装置の断面図、第2図は、本考案の
第2の実施例を示す紫外線消去型半導体記憶装置
の断面図、第3図は、従来のP・PGA型半導体
装置の断面図、第4図は、従来の紫外線消去型半
導体記憶装置の断面図である。 1…絶縁性容器、1a…ベース、1b…外枠、
2…半導体チツプ、3…ピン、4…キヤツプ、5
…樹脂A、6…ワイヤ、7…引出導体、8…樹脂
B、9…マウント材、10…マウント面、11…
側壁面、11′…傾斜した側壁面、12…ガラス
キヤツプ、13…低融点ガラス、14…リードピ
ン、15…枠、16…接着樹脂、17…スルーホ
ール、18…絶縁性容器の平面、19…半導体チ
ツプの端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チツプを載置するマウント面を底面とす
    る凹部を備えた絶縁性容器と、前記絶縁性容器に
    被せて封止するキヤツプとを有する半導体装置に
    おいて、前記絶縁性容器の凹部には、前記底面に
    対して傾斜した側壁面に前記半導体チツプの端子
    とを結線する引出導体が設けられていることを特
    徴とする半導体装置。
JP305589U 1989-01-13 1989-01-13 Pending JPH0295246U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP305589U JPH0295246U (ja) 1989-01-13 1989-01-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP305589U JPH0295246U (ja) 1989-01-13 1989-01-13

Publications (1)

Publication Number Publication Date
JPH0295246U true JPH0295246U (ja) 1990-07-30

Family

ID=31204353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP305589U Pending JPH0295246U (ja) 1989-01-13 1989-01-13

Country Status (1)

Country Link
JP (1) JPH0295246U (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998049726A1 (fr) * 1997-04-30 1998-11-05 Hitachi Chemical Company, Ltd. Plaquette pour monter un element a semi-conducteur, procede permettant de la produire et dispositif a semi-conducteur
US6617193B1 (en) 1997-04-30 2003-09-09 Hitachi Chemical Company, Ltd. Semiconductor device, semiconductor device substrate, and methods of fabricating the same
JP2017059757A (ja) * 2015-09-18 2017-03-23 日本電気株式会社 半導体装置および半導体装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998049726A1 (fr) * 1997-04-30 1998-11-05 Hitachi Chemical Company, Ltd. Plaquette pour monter un element a semi-conducteur, procede permettant de la produire et dispositif a semi-conducteur
US6268648B1 (en) 1997-04-30 2001-07-31 Hitachi Chemical Co., Ltd. Board for mounting semiconductor element, method for manufacturing the same, and semiconductor device
US6617193B1 (en) 1997-04-30 2003-09-09 Hitachi Chemical Company, Ltd. Semiconductor device, semiconductor device substrate, and methods of fabricating the same
CN100370602C (zh) * 1997-04-30 2008-02-20 日立化成工业株式会社 半导体元件装配用基板及其制造方法和半导体器件
JP2017059757A (ja) * 2015-09-18 2017-03-23 日本電気株式会社 半導体装置および半導体装置の製造方法

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