JPH0340948B2 - - Google Patents

Info

Publication number
JPH0340948B2
JPH0340948B2 JP58233125A JP23312583A JPH0340948B2 JP H0340948 B2 JPH0340948 B2 JP H0340948B2 JP 58233125 A JP58233125 A JP 58233125A JP 23312583 A JP23312583 A JP 23312583A JP H0340948 B2 JPH0340948 B2 JP H0340948B2
Authority
JP
Japan
Prior art keywords
groove
polycrystalline silicon
forming
film
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58233125A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60124840A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP23312583A priority Critical patent/JPS60124840A/ja
Publication of JPS60124840A publication Critical patent/JPS60124840A/ja
Publication of JPH0340948B2 publication Critical patent/JPH0340948B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
JP23312583A 1983-12-09 1983-12-09 半導体装置の製造方法 Granted JPS60124840A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23312583A JPS60124840A (ja) 1983-12-09 1983-12-09 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23312583A JPS60124840A (ja) 1983-12-09 1983-12-09 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS60124840A JPS60124840A (ja) 1985-07-03
JPH0340948B2 true JPH0340948B2 (enrdf_load_stackoverflow) 1991-06-20

Family

ID=16950142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23312583A Granted JPS60124840A (ja) 1983-12-09 1983-12-09 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS60124840A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583065A (en) * 1994-11-23 1996-12-10 Sony Corporation Method of making a MOS semiconductor device
JPH113936A (ja) 1997-06-13 1999-01-06 Nec Corp 半導体装置の製造方法
US6221735B1 (en) * 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882532A (ja) * 1981-11-11 1983-05-18 Toshiba Corp 素子分離方法
JPS58168259A (ja) * 1982-03-30 1983-10-04 Nippon Telegr & Teleph Corp <Ntt> 半導体集積回路装置の製造方法

Also Published As

Publication number Publication date
JPS60124840A (ja) 1985-07-03

Similar Documents

Publication Publication Date Title
US5763315A (en) Shallow trench isolation with oxide-nitride/oxynitride liner
US6747333B1 (en) Method and apparatus for STI using passivation material for trench bottom liner
US5989978A (en) Shallow trench isolation of MOSFETS with reduced corner parasitic currents
JPH0834242B2 (ja) 半導体装置およびその製造方法
JPH08330305A (ja) 半導体装置の絶縁膜形成方法
US6475865B1 (en) Method of fabricating semiconductor device
JPS6231116A (ja) 半導体装置の製造方法
JPS62106644A (ja) 半導体構造形成方法
US5114875A (en) Planar dielectric isolated wafer
US6096622A (en) Method of forming shallow trench isolation of semiconductor device
JPH04303942A (ja) 半導体装置の製造方法
JPH0340948B2 (enrdf_load_stackoverflow)
KR100428526B1 (ko) 절연체상실리콘기술을위한분리산화물을형성하는방법
JP3153632B2 (ja) Ｓｏｉ構造の製造方法
US6849493B2 (en) Methods of forming polished material and methods of forming isolation regions
JP2552936B2 (ja) 誘電体分離基板およびこれを用いた半導体集積回路装置
JPS6020530A (ja) 素子分離領域の形成方法
US6316330B1 (en) Method of fabricating a shallow trench isolation semiconductor device
US6500729B1 (en) Method for reducing dishing related issues during the formation of shallow trench isolation structures
JP2000183150A (ja) 半導体装置の製造方法
CN1257609A (zh) 制造平面沟槽的方法
JPS60124839A (ja) 半導体装置の製造方法
KR950009888B1 (ko) 반도체장치의 제조방법
US6261966B1 (en) Method for improving trench isolation
JP2669724B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees