JPH0338734B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MOS type semiconductor device, and particularly to a method for manufacturing a MOS type semiconductor device using a high melting point metal as a gate electrode material.

MOS type semiconductor devices that use high-melting point metals such as Mo, W, and Pt as gate electrode materials have lower electrical conductivity than conventional silicon gates that use impurity-doped polysilicon as gate electrodes. It has advantages such as large size and high processing accuracy. However, on the other hand, it has the disadvantage that it is weak against oxidizing atmospheres and cannot undergo a step in an oxidizing atmosphere after growing a metal with a high melting point. or,
It has the disadvantage that the reaction between the high melting point metal and the substrate Si occurs easily and continues without stopping. Therefore, in circuits where the high melting point metal of the gate needs to be directly connected to the Si substrate, a buried contact method is used in ordinary silicon gate MOS;
This is not possible with MOS, and the gate metal and the metal connected to the Si substrate are made using separate metals and are connected later. However, this method has drawbacks such as an increased number of photo-etching steps, a longer process, and a larger occupied area.

The present invention eliminates the above-mentioned drawbacks and is a method for manufacturing a refractory metal MOS in which a buried contact of the refractory metal MOS can be formed in a process substantially equivalent to that of a normal silicon gate MOS.

That is, in the present invention, the reaction between the substrate Si and the high-melting point metal is prevented during the formation of the buried contact and subsequent steps, and the high-melting point metal is exposed to an oxidizing atmosphere at a high temperature after growth. We have proposed a unique manufacturing method that makes it possible to form such buried contacts.

The details of the present invention will be described below using the drawings.

As an example, consider the MOS inverter circuit shown in FIG. 1 is a depression type load
MOS transistor 2 is an enhancement type drive MOS transistor. The method of wiring connecting the gate electrode 3 of the load MOS transistor and the source 4 of the load MOS transistor is particularly problematic.

Conventionally, the method for manufacturing a high melting point metal gate MOS semiconductor device to realize the circuit shown in FIG.
As shown in Figure 2. That is, a silicon oxide film 6 and a silicon nitride film 7 are formed on a silicon substrate 5, and a thick field oxide film 8 is formed on the non-active region by photolithography and subsequent selective oxidation (FIG. 2a). Next, the silicon nitride film 7 and the silicon oxide film 6 are etched, and the gate oxide film 6' is re-etched.
Then, a high melting point metal film 9 is formed (FIG. 2b). Next, the high melting point metal film 9 and the gate oxide film 6' are selectively etched, and a diffusion layer 10 is formed by ion implantation or the like (FIG. 2c). Next, the phosphor silicon glass film 11
form. (Figure 2d). Finally, the phosphor-silicon glass film 11 is selectively etched and then the metal wiring 12 is formed (FIG. 2e) to complete the inverter circuit shown in FIG. 1. Since the wiring from 3 to 4 shown in FIG. 1 is conducted through the contact openings 13 and 14 by the metal wiring 12, the area occupied by the entire circuit increases by the area occupied by the contact openings.

FIG. 3 shows a high melting point metal gate for realizing the inverter circuit of FIG. 1 according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a method of manufacturing a MOS semiconductor device.
Similar to the conventional method shown in FIG. 2, a silicon oxide film 6 and a silicon nitride film 7 are formed on a Si substrate 5, and photolithography and selective oxidation are performed to form a thick silicon oxide film 8 on non-active regions. (Figure 3a). Next, silicon nitride film 7 and silicon oxide film 6 are etched to form a new gate oxide film 6' and silicon nitride film 7'. (Figure 3b). Next, an opening 15 is formed by photolithography at a portion where contact with the silicon substrate is to be formed, and an impurity doped layer 16 is formed by ion implantation or the like on the Si substrate in the opening (FIG. 3c).
Next, the silicon nitride film 7' is etched with phosphoric acid or the like, and a high melting point metal 9 is again formed on the entire surface (FIG. 3d). Next, patterning is performed by photolithography to obtain the shape shown in FIG. 3e. Next, a diffusion layer 10 is formed by ion implantation or the like (FIG. 3f).
Next, a phosphosilicon glass film 11 is formed in the same manner as in the conventional method, selective etching is performed (FIG. 3g), and finally metal wiring is formed to complete the inverter circuit (FIG. 3h).

According to the present invention, the contact openings 13 and 1 for wiring from 3 to 4 shown in FIG.
4 becomes unnecessary. Therefore, it is possible to realize an inverter circuit that occupies a smaller area than the conventional method. In the present invention, as shown in FIGS. 3c to 3e, a high melting point metal contact is drawn out in the Si layer 16 which has been previously diffused. In this way, it becomes possible to suppress the reaction between Si and the high melting point metal. As shown in Figure 4, the reaction layer between Si and high melting point metal is Si
The lower the impurity concentration, the greater the impurity concentration. Furthermore, Fig. 3 f to h
As shown in Figure 2, the process that is exposed to high temperatures after the growth of a high-melting point metal is the annealing after ion implantation to form a diffusion layer (900°C to 1000°C for 5 minutes), but it is not possible to do this in an inert gas or nitrogen atmosphere. The impurity doped layer 10 in the present invention does not have an adverse effect on the high melting point metal or the contact area between the high melting point metal and the substrate Si.
16 etc. may be formed by ion implantation or thermal diffusion. However, in the thermal diffusion method, it is necessary to etch the silicon oxide film formed during thermal diffusion, which tends to cause pinholes in the gate oxide film under the high melting point metal, resulting in poor withstand voltage. Therefore, ion implantation is more desirable.

[Brief explanation of drawings]

FIG. 1 is an inverter circuit diagram, FIGS. 2a to 2e are cross-sectional views showing the conventional manufacturing method in order of process for realizing the inverter circuit in FIG. 1, and FIG.
Figures a to 3h are cross-sectional views showing the steps of the manufacturing method according to the embodiment of the present invention, and Figure 4 shows the relationship between (the thickness of the reaction layer between the high melting point metal and the substrate silicon) and (the impurity concentration of the substrate silicon). It is a figure showing a relationship. In the figure, 1...Load MOS transistor, 2...Drive MOS transistor, 3...Load
Gate electrode of MOS transistor, 4...Load
Source of MOS transistor, 5...Substrate silicon, 6...Silicon oxide film, 6'...Gate oxide film, 7...Silicon nitride film, 7'...Silicon nitride film on gate oxide film, 8...Field Oxide film, 9... High melting point metal film, 10... Diffusion layer, 11
... Phosphorus silicon glass film, 12 ... Metal wiring, 1
3, 14...Contact opening, 15...Substrate Si
The opening of the part forming the contact with, 16...
This is an impurity-doped layer that forms contact with the silicon substrate.

Claims (1)

[Claims] 1. A step of selectively forming a first impurity doped region of another conductivity type on one main surface of a semiconductor substrate of one conductivity type, and a step of forming the first impurity doped region on one side of the first impurity doped region. a high melting point metal extending from the first impurity doped region on a first insulating film selectively provided on the first impurity doped region with its bottom end in contact with the top end of the first impurity doped region; selectively forming a first wiring region on the other side of the main surface with respect to the first impurity doped region in proximity to the first impurity doped region; selectively forming a second wiring region made of a high-melting point metal on the second insulating film, and selecting the first wiring region and the second wiring region on the one main surface using the first wiring region and the second wiring region as masks; By introducing an impurity of another conductivity type into the first insulating film,
A second main surface on the opposite side to the impurity doped region.
The impurity doped region is placed on the one main surface on the same side as the first impurity doped region with respect to the second insulating film, and the upper surface of the end on the second insulating film side is the second insulating film.
a third impurity doped region that is in contact with an end of the bottom surface of the insulating film on the first impurity doped region side and whose end on the first impurity doped region side overlaps a part of the first impurity region; A method for manufacturing a semiconductor device, comprising the step of providing a fourth impurity doped region on the one main surface of the second insulating film opposite to the third impurity doped region.