JPH0334258B2 - - Google Patents

Info

Publication number
JPH0334258B2
JPH0334258B2 JP3134278A JP3134278A JPH0334258B2 JP H0334258 B2 JPH0334258 B2 JP H0334258B2 JP 3134278 A JP3134278 A JP 3134278A JP 3134278 A JP3134278 A JP 3134278A JP H0334258 B2 JPH0334258 B2 JP H0334258B2
Authority
JP
Japan
Prior art keywords
clock
clock signal
logic circuit
delay time
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3134278A
Other languages
English (en)
Japanese (ja)
Other versions
JPS54123977A (en
Inventor
Masaaki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3134278A priority Critical patent/JPS54123977A/ja
Publication of JPS54123977A publication Critical patent/JPS54123977A/ja
Publication of JPH0334258B2 publication Critical patent/JPH0334258B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
JP3134278A 1978-03-17 1978-03-17 Logic circuit apparatus Granted JPS54123977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3134278A JPS54123977A (en) 1978-03-17 1978-03-17 Logic circuit apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3134278A JPS54123977A (en) 1978-03-17 1978-03-17 Logic circuit apparatus

Publications (2)

Publication Number Publication Date
JPS54123977A JPS54123977A (en) 1979-09-26
JPH0334258B2 true JPH0334258B2 (enrdf_load_stackoverflow) 1991-05-22

Family

ID=12328550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3134278A Granted JPS54123977A (en) 1978-03-17 1978-03-17 Logic circuit apparatus

Country Status (1)

Country Link
JP (1) JPS54123977A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS54123977A (en) 1979-09-26

Similar Documents

Publication Publication Date Title
EP0136204B1 (en) Control of signal timing apparatus in automatic test systems using minimal memory
US4878209A (en) Macro performance test
US4789835A (en) Control of signal timing apparatus in automatic test systems using minimal memory
US4837521A (en) Delay line control system for automatic test equipment
US4385275A (en) Method and apparatus for testing an integrated circuit
JP2574194B2 (ja) デジタル・パルス発生装置
US4370619A (en) Phase comparison circuit arrangement
US3047841A (en) Marginal checking means for electrical pulse circuits
JPH0334258B2 (enrdf_load_stackoverflow)
JP2001273794A (ja) フェイル前情報取得回路およびその取得方法
EP0585086A2 (en) Method and apparatus for self-testing of delay faults
US6378092B1 (en) Integrated circuit testing
US5315242A (en) Method for measuring AC specifications of microprocessor
US4847616A (en) Mode selection circuit
JP2936807B2 (ja) 集積回路
JPS5814989B2 (ja) ロジック素子あるいはロジック回路の動作速度試験回路
JPS61286768A (ja) テスト装置
SU1684756A1 (ru) Устройство дл функционального контрол цифровых интегральных схем
JPS5538604A (en) Memory device
JP2846383B2 (ja) 集積回路試験装置
JPH01180055A (ja) チャネルインタフェース折返し試験方式
JPS6045375B2 (ja) Ic試験器用タイミング発生装置
JPS61126481A (ja) デイジタルパタ−ンテスタ
JPS6037560B2 (ja) フエイルメモリ書込み方式
JPH0434703B2 (enrdf_load_stackoverflow)