JPH0334219B2 - - Google Patents

Info

Publication number
JPH0334219B2
JPH0334219B2 JP2023985A JP2023985A JPH0334219B2 JP H0334219 B2 JPH0334219 B2 JP H0334219B2 JP 2023985 A JP2023985 A JP 2023985A JP 2023985 A JP2023985 A JP 2023985A JP H0334219 B2 JPH0334219 B2 JP H0334219B2
Authority
JP
Japan
Prior art keywords
terminal
light emitting
semiconductor light
stem header
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2023985A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61179558A (ja
Inventor
Yoichiro Nabeshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2023985A priority Critical patent/JPS61179558A/ja
Publication of JPS61179558A publication Critical patent/JPS61179558A/ja
Publication of JPH0334219B2 publication Critical patent/JPH0334219B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/045Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2023985A 1985-02-05 1985-02-05 半導体装置の容器 Granted JPS61179558A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023985A JPS61179558A (ja) 1985-02-05 1985-02-05 半導体装置の容器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2023985A JPS61179558A (ja) 1985-02-05 1985-02-05 半導体装置の容器

Publications (2)

Publication Number Publication Date
JPS61179558A JPS61179558A (ja) 1986-08-12
JPH0334219B2 true JPH0334219B2 (cg-RX-API-DMAC7.html) 1991-05-21

Family

ID=12021641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023985A Granted JPS61179558A (ja) 1985-02-05 1985-02-05 半導体装置の容器

Country Status (1)

Country Link
JP (1) JPS61179558A (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288379A (ja) * 2007-05-17 2008-11-27 Toshiba Corp 半導体パッケージ
JP5409456B2 (ja) * 2009-07-28 2014-02-05 京セラ株式会社 電子部品搭載用パッケージおよびそれを用いた電子装置
US10319654B1 (en) * 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages

Also Published As

Publication number Publication date
JPS61179558A (ja) 1986-08-12

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