JPH032926A - Microsequence circuit - Google Patents

Abstract

PURPOSE:To increase the number of microprocommands without increasing the number of microprogram store memories and process steps by producing an instruction so as to produce a 2nd microcommand from the data stored in an instruction extension register prepared by a controller and in response to a 1st microcommand. CONSTITUTION:A microinstruction stored in an instruction register 2 is decoded and a 1st microcommand is produced by a 1st decoder 9. A pointing flip-flop 12 works in response to the 1st microcommand, and the data prepared by a controller are stored in an instruction extension register 10. Then the flip-flop 12 gives an instruction to a 2nd decoder 11 so as to produce a microcommand from the data stored in the register 10. Thus the prepared data are stored in the register 10 and a microcommand is set by the flip-flop 12. As a result, the number of produced microcommands is increased together with reduction of the number of microprogram store memories and process steps.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microsequence circuit, and particularly to a microsequence circuit that uses vertical microinstructions to control the operation of an information processing device.

[Prior Art] Conventionally, in this type of vertical microsequence circuit, when there is a shortage of microcommands for operating a control device, this shortage is compensated for by executing a plurality of microcommands.

[Problems to be Solved by the Invention] The above-described conventional vertical microsequence circuit is configured to execute multiple microinstructions when one microinstruction cannot control the desired operation. Therefore, there are drawbacks such as an increase in microprogram storage memory due to an increase in the number of microprograms that control the control device, and a decrease in performance due to an increase in the number of processing steps.

An object of the present invention is to provide a microcommand circuit that can increase the number of microcommands without increasing the number of microprogram storage memories and the number of processing steps.

[Means for Solving the Problems] In order to achieve the above object, a microsequence circuit according to the present invention has the following features.

That is, the present invention provides, in a microsequence circuit of a control device constituting an information processing device controlled by microprogramming, a memory that stores a microprogram, an instruction register that stores a microinstruction read from the memory, and the instruction. a first decoder that decodes the microinstruction stored in a register and generates a first microcommand; an instruction extension register that stores data prepared by the control device; and data stored in the instruction extension register. a second decoder that generates a second microcommand from a second microcommand; and an instruction flip-flop that instructs the second decoder to generate a second microcommand in response to the first microcommand. It is characterized by

[Operation] When the first decoder generates the first microcommand, the instruction flip-flop operates in accordance with the microcommand, and data prepared by the control device is stored in the instruction extension register. An instruction flip-flop instructs the second decoder to generate a microcommand from the data in the instruction extension register.

By the above, the number of microcommands can be increased.

[Example] Next, the present invention will be described in detail with reference to the drawings.

The drawing is a block diagram of a microsequence circuit according to an embodiment of the present invention, which is installed in a control device 60.

The microsequence circuit of this embodiment includes the following. Memory that stores microprograms (C
3) 1° Register (MIR) that stores the microinstruction read out from memory 1 2° Adder (+1) that generates the next address of the address to be read from memory 1 (that is, the address +1) 3° adder Address register (MAR) that stores the output of 3. 4° Address stack memory (RTA) that stores the return address when the microsequence is switched by executing a jump instruction or by accepting an interrupt in a 4° microsequence. 5° Jump Adder (±K) that obtains the jump destination address when executing an instruction 6° Interrupt control circuit that controls interrupt enable/disable when an interrupt signal is accepted and generates an interrupt address when interrupt is enabled 7° Address Register 4, address stack memory 5, adder 6
, a switching circuit (MPX) that receives address information from the register 2 and the address bus 200, and controls switching of address information in the memory 1 for microsequence control based on instructions from the interrupt control circuit 7.
8° A first decoder (which generates a microcommand (CMDA) 50 from the microinstruction stored in register 2)
DECI) 9° Instruction Extension Register (EMIR) IQ that stores data prepared by controller 60. A second decoder (DEC2) generates a microcommand (CMDE) 51 from the data stored in the instruction extension register 10.
) 11° An instruction flip-flop (F) which is controlled by a microcommand (CMDA) 50 and permits/disallows generation of a microcommand 51 based on data stored in the instruction extension register 10; An arithmetic circuit 20° for performing various calculations; a data bus 100° inside the control device 60; and an address bus 200 also inside the control device 60.

Next, operation control in this invention will be explained. Regarding a certain operation of the control device 60, the following three operations are assumed.

(1) Operation a; The contents of the A register and the contents of the B register are calculated, and the result of the calculation is manually input to the C register.

(2) Operation b=move the contents of the D register to the E register.

(3) Operation C: Transfer the contents of the C register to the D register.

The microinstruction read into register 2 does not have the data width to generate microcommands to process operations a, b, and c simultaneously, so in conventional vertical microsequence circuits, the three operations are performed in sequence. was. However, since operations a and b do not conflict with each other for register resources, they may originally be executed simultaneously.

Therefore, in this invention, the following steps are taken.

The instruction extension register 10 stores data for generating a microcommand for performing operation b, and the register 2 stores a microinstruction for executing operation a. At this time, it is assumed that an instruction is given to set the instruction flip-flop 12 (it is assumed that the instruction to set the instruction flip-flop 12 is given in a microinstruction before executing operation a). Then, a microcommand 50 for executing operation a is sent from the first decoder 9, and at the same time a microcommand 51 for executing operation b is sent from the second decoder 11, and operations a and b are executed simultaneously. Next, operation C is executed, and this execution is performed using register 2.

The microinstruction to execute operation a includes:
An instruction for resetting the instruction flip-flop 12 is also added.

Conventionally, three microinstructions for executing operations a, b, and c were stored in a register one after another to execute the three operations.

However, in this embodiment, the instruction extension register 10
, the instruction flip-flop 12, and the second decoder 11, the register 2 stores the operation a.
It is only necessary to store two microinstructions corresponding to the SC.

In order to explain one embodiment of this invention, three simple operations have been explained as an example, but even in the case of more complicated control, if there are no competing resources,
It is clear that multiple operations can be accomplished in a similar manner with fewer operations.

Next, the instruction extension register 10 and the instruction flip-flop 1
The control method with 2 will be explained in detail.

The data to the instruction extension register 10 is the data bus]00
supply more. An instruction to sequentially store data prepared in advance in a work memory (not shown) or the like in the control device 60 in the instruction extension register 10 is given by a microinstruction stored in the register 2. If you need to perform high-performance processing for a certain period of time, do the following: A microinstruction stored in the register 2 specifies that the instruction flip-flop 12 is reset after being set for a certain period of time. As a result, it is expected that the number of microcommands will increase during this period. The instruction flip-flop 12 does not necessarily need to be reset by a microcommand. It may also be reset as a result of a hardware operation.

[Effects of the Invention] As explained above, the present invention solves the disadvantage of vertical microsequence circuits in that the number of microcommands generated per one step is small, by storing previously prepared data in the instruction extension register. This problem is solved by controlling the setting of microcommands using an instruction flip-flop and increasing the number of microcommands to be generated. As a result, the present invention can reduce the microprogram storage memory and the number of processing steps. This has the effect of reducing the cost of the microsequence circuit and improving its performance.

[Brief explanation of the drawing]

The drawing is a block diagram of a microsequence circuit according to an embodiment of the present invention. 1...Memory for storing microprograms 2...
Register (instruction register) 9...First decoder 10...Instruction extension register 11...Second decoder 12...Instruction flip-flop 50...Microcommand<"J-microcommand" 51 ...Microcommand (second microcommand) 60...Control device

Claims (1)

[Scope of Claim] A microsequence circuit of a control device constituting an information processing device controlled by microprogramming, comprising: a memory that stores a microprogram, an instruction register that stores a microinstruction read from the memory, and the instruction. a first decoder that decodes the microinstruction stored in a register and generates a first microcommand; an instruction extension register that stores data prepared by the control device; and data stored in the instruction extension register. a second decoder that generates a second microcommand from , and an instruction flip-flop that instructs the second decoder to generate a second microcommand in response to the first microcommand. A microsequence circuit characterized by: