JPS6024643A - Microprogram controlling system - Google Patents

Abstract

PURPOSE:To reduce the number of steps for executing a program by setting a branch destination address to one, in case a value (i) of a plural condition signal is larger or smaller than a value (m) designated by a micro-instruction word. CONSTITUTION:When a value of a plural condition signal and a value of a constant field B are denoted as (i) and (m), respectively, and (i)<(m), a comparison result signal 300 is not outputted, and the plural condition signal, and the minimum value of the plural condition signal 100 are outputted to an OR500 and an AND800, respectively. Accordingly, when a mode signal 204 is ''1'' and ''0'', a value which an address signal 700 can designate is (m) kinds or one kind. On the other hand, in case of (i)>=(m), the comparison result signal 300 is outputted, and the maximum value that the plural condition signal 100 can designate, and the plural condition signal 100 are outputted to the OR500 and the AND800, respectively. Accordingly, when the mode signal 204 is ''1'' and ''0'', the value which the address signal 700 can designate is one kind or (m) kinds. Accordingly, as for a branch desitnation micro-instruction, it will do that (m)+1 pieces are prepared.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a microprogram control system in a data processing device, and particularly to a multidirectional branch control system using a microprogram.

[Prior art]

In the conventional multidirectional conditional branch control system using microinstructions, if the possible values of a plurality of conditional signals are n, there are n branch destination addresses.

Therefore, the microprogram processing after branching is different when i≦m, m (same when i≦n), where the value i of the multiple condition signal is the value specified by the microinstruction word and m is the value specified by the microinstruction word. Even when After that, multidirectional branching based on multiple conditional signals must be performed, resulting in an increase in the number of steps in microprogram execution.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks by setting a single branch destination address when the value i of a plurality of conditional signals is greater than or less than the value m specified by a microinstruction word. purpose.

[Structure of the invention]

According to the present invention, a constant field having a value to be compared with the values of a plurality of condition signals and a mode pit for specifying a comparison method are provided in a microinstruction word, and the value of the plurality of condition signals and the constant field are provided. a comparison means for comparing the values with the values and outputting a comparison result; and if the comparison result of the comparison means is that the value of the constant field is larger and the mode pit is logic '11, the value of the address field in the microinstruction word is A plurality of pits among them are replaced with the plurality of condition signals and output as the next microinstruction address, and if the value of the constant field is smaller or equal and the mode pit is logic 111, the plurality of bits of the address field are replaced with the plurality of condition signals and output as the next microinstruction address. The value replaced by the maximum possible value of the plurality of condition signals is output as the next microinstruction address, and if the value of the constant field is smaller or equal and the mode pit is logic 101, the plurality of the address fields The bits replaced with the plurality of condition signals are output as the next microinstruction address, and if the value of the constant field is larger and the mode pit is logic 10.
In this case, there is obtained a microprogram control system characterized in that it includes a switching means for replacing the plurality of bits of the address field with the minimum value that the plurality of condition signals can take and outputting the result as the next microinstruction address. .

[Explanation of Examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention,
FIG. 2 is a diagram showing the format of the microinstruction word for controlling this. In FIG. 1, 1 is a control storage device, and 2 is a microinstruction register.

3 is a comparison circuit, 4 is a decoder, 5 is an OI (circuit), 6 is a switching circuit, 8 is an AND circuit, and 9 is a switching circuit, which are set in the microinstruction register 2.The microinstruction words are as shown in FIG. , a data processing section operation specification field A that specifies various operations of the data processing section, a constant field B that specifies the value to be compared with the value of a plurality of condition signals, a mode pit C that specifies the comparison method, and a microprogram. It has a sequence control field D, and an address field E that specifies the address of the microinstruction to be executed next.

The data processing section operation designation field is sent as a microcommand to the data processing section (not shown). Multiple condition signals 100 and constant field 200 sent from the data processing unit based on the execution results of the previous microinstructions
are input to the comparison circuit 3, and if the former value is larger, a comparison result signal 300 is output. The OR circuit 5 takes the logical sum of the comparison result signal 300 and each of the multiple condition signals 100, and the resulting sum signal 500 is sent to the switching circuit 9.
This is one of the inputs. In the AND circuit 8, the comparison result signal 3
00 and each of the plurality of condition signals 100 is taken, and the resulting product value, 800, becomes the other input of the switching circuit 900. The switching circuit 9 changes the sum signal 500 to "0" when the mode signal 204 from the mode pin C is logic "1".
", the product signal 800 is output as a signal 900 and sent to one input of the switching circuit 6. A plurality of bits 202 of the output bits of the address field E are input to the other input of the switching circuit 6. The output signal of the sequence control field D is input to the decoder 4, and if multi-directional branching is specified, a switching signal 400 is input.
is output from the decoder 4, and a plurality of bits 202 of the output bits of the address field E are switched to the signal 900 to become the signal 600. If a multidirectional branch is not specified, switching signal 400 is not output, and signal 600 contains multiple bits of the output bits of address field E.
202 is output. The switching circuit 7 switches between the signal 600, the remaining bit 203 of the output bits of the address field E, and other signals (interrupt address, increment address, etc.) 50, and outputs the next microinstruction address signal 700. However, it is not related to the present invention and will not be explained in detail.

As described above, if multidirectional branching is not specified in the 7-case control field, the switching signal 400 is not output, and therefore the address field is sent.

When multi-directional branching is specified in the sequence control field, a switching signal 400 is output, but if the value of the multiple condition signal 100 is i and the value of the constant field is m, then i
'(When m, the comparison result signal 300 is not output, so the multiple condition signal 100 is output as is as the sum signal 500, and the minimum value that the multiple condition signal 1()0 can take is output as the product signal 800. Therefore, when the mode signal 204 is logic "1", the address signal 700 has a plurality of condition signals 1.
00 and the remaining bits 203 of the output bits of address field E are output. The address signal 700 at this time can have m values in the former case, and 1 value in the latter case.

On the other hand, when i>m, the comparison result signal 300 is output, the maximum value of the multiple condition signal 100 is output as the sum signal 500, and the multiple condition signal 100 is output as is as the product signal 8001C. Therefore, mode signal 204 is logic Il.
When l, the address signal 700 has multiple conditions - No. 100.
The maximum possible value of the address field E and the remaining bits 203 of the output bits are output, and when it is '0'', the multiple condition signal 100 and the remaining bits 203 of the address field E output bits are output. The value of the address signal 700 at this time is 1 in the former case.
In the latter case, there are m ways.

From the above, it is sufficient to prepare m+1 branch destination microinstructions, which reduces the amount of microprograms and does not require an increase in the number of steps since it is not necessary to determine i(m in advance).

〔Effect of the invention〕

According to the present invention, as described above, multi-directional branching control can be easily performed with a small number of microprogramming steps.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 23...-
... Comparison circuit, 4 ... Decoder, 5 ...
...0 circuit, 6...switching circuit, 8...
・AND circuit, 9・−・−・switching circuit.

Claims (1)

[Claims] a constant field having a value to be compared with a plurality of condition signal values in a microinstruction word, a comparison means for specifying a comparison method, and a comparison result of the comparison means is such that the value of the constant field is larger and the If the mode pit is logic "1", the internal machine number bit in the address field in the microinstruction word is replaced with the plurality of condition signals and output as the next microinstruction address, and the value in the constant field is higher than the value in the constant field. less than or equal to and the mode pit is logic “1”
If the value of the constant field is smaller or equal to the value of the constant field and the mode pit is logic 10", the plurality of bits of the address field are replaced with the plurality of condition signals and output as the next microinstruction address, and the value of the constant field is larger and the mode pit is logic "0". "In the case of ", the plurality of bits of the address field are replaced with the minimum value that the plurality of condition signals can take, and the result is output as the next microinstruction address.