JPS6320536A - Information processor - Google Patents

Abstract

PURPOSE:To execute the processing at a high speed by executing preferentially that which requires a result as soon as possible, in case of a competition between a computing element output in the same computing element and an added pipeline use register output, or otherwise, executing preferentially an output from the latter stage of the pipeline use register. CONSTITUTION:At the time of a selective control of a switching circuit 12, when there is a competition of outputs of the maximum 4 cases of a result of an adder and subtracter circuit system, which is to be executed preferentially is determined, and unless that which desires to output a result as soon as possible especially exists, the degree of priority becomes higher as to that of the latter stage of the pipeline. Also, when that which desires to output the result as soon as possible especially exists, for instance, when an instruction for using its result as an operand is waiting for the execution, the result is stored in an arithmetic operation register 16 immediately. Unless it is read out and executed, a fall of the performance is caused, therefore, even when other result is not transferred yet to the arithmetic operation register 16 but left in the pipeline use register of the latter stage side than said one, this result overruns it and stored in the arithmetic operation register 16 if it is allowed. A switching circuit 13 is also constituted in the same way as the switching circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pipelined information processing device, and particularly to a pipelined information processing device that executes a plurality of instructions in parallel.

[Conventional technology]

In general, in information processing equipment that pursues high performance, each independent computing unit is made into an online system, and operands are continuously sent to the same computing unit for similar operations. Igraine processing.

For different operations, operands are continuously sent to different arithmetic units and processed in parallel. In addition, each type of arithmetic unit is realized with the least number of pipeline stages to improve performance.

[Problem that the invention seeks to solve]

However, for the same arithmetic unit, - due to quisi-line processing, the arithmetic results are output sequentially in the order of input, - results from different arithmetic units are output depending on the input timing of operands to each arithmetic unit, and the timing of inputting operands to each arithmetic unit. Due to the difference in the number of pipeline stages, there may be conflicts at the same timing. The calculation results are generally stored in the software visible register group (hereinafter referred to as the calculation register), but since this is usually stored in memory, it is not possible to store multiple results at the same timing. Can not.

To avoid this, calculate backwards from the number of pipeline stages of each arithmetic unit, and if there is a conflict in the output timing of the result, appropriately delay the input timing of operands to each arithmetic unit, that is, the start of instruction execution. There is. In devices that employ a control method that allows instructions to be executed only in the order of a given instruction sequence.

By delaying the start of execution of the 1 instruction, subsequent instructions are also sequentially delayed, resulting in a decrease in performance.

[Means for solving problems]

The information processing device of the present invention has a plurality of pipelined arithmetic units with different functions, and when the minimum number of stages required for each operation is different, the following stage is used for each arithmetic unit. Is there a register for each calculation system that only transfers device results? Add the necessary number of stages so that the number of stages of the ideal line is equal, and select one of the switching means that can output the operation result from any register of the added registers for the ideal line, and the output of all results. If there is a conflict between the arithmetic unit output of the same arithmetic unit and the added pipeline register output, if there is one that requires the result quickly, this will take priority, otherwise the pipeline register and a control means for prioritizing the output from the subsequent stage.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 and 2 are block diagrams and partially detailed views of one embodiment of the present invention. In Figure 1.

Multiplication circuit 1. Addition/subtraction circuit 2. Each logic operation circuit 3 has 7. Each stage is a pipelined arithmetic unit that operates in one machine cycle, and it is possible to process a different fourth land calculation every machine cycle in a noquizoline manner. Furthermore, when the operands necessary for each operation are given through the input obelandnoxes 1001 and 1002, the busy operation results can be output after 7 machine cycles, 4 machine cycles, and 2 machine cycles, respectively.

The number of stages of the addition/subtraction circuit 2 and logic operation circuit 3 is 4 stages and 2 stages, respectively. The number of pipeline stages is 17, so there is a difference.

(Tsum) 3-stage and 5-stage /give line registers 4~
6, 7 to 11 are connected to the addition/subtraction circuit 2 and the logic operation circuit 3.

The switching circuit 12 is a circuit that selects and outputs either the output of the addition/subtraction circuit 2 or the output of the pipeline registers 4 to 6, and the switching circuit 13 selects and outputs the output of the logic operation circuit 3.
This circuit selects and outputs one of the outputs of the twin line registers 7 to 11. Also, the switching circuit 14
selects one of the outputs of the multiplier circuit 1° switching circuit 12 and 13 and writes it to the calculation register 16.
This is a circuit that outputs to 03.

In this embodiment, the multiplier circuit 1 is not provided with a pipeline register, but this is for the purpose of simplifying the explanation. Similar to the logic operation circuit 3, an appropriate number of pipeline registers may be provided at the subsequent stage. In this case, the number of stages of pipeline registers provided in the multiplication circuit is
Addition/subtraction circuit.

This also increases the number of stages of pipeline registers in the logical operation circuit.

The control circuit 15 is a circuit that controls selection of the switching circuits 12, 13, and 14. First, the selection control of the switching circuit 14 is to determine which arithmetic circuit system will give priority to the output when a conflict occurs in the output of the result between the arithmetic circuit systems, and the priority order is the multiplier circuit system. , addition/subtraction circuit system, and logic operation circuit system.

For example, the multiplier circuit does not have a register for the multiplier line, so as soon as the result is obtained, the arithmetic register 16
Since the result will be lost if it is not transferred, it is given the highest priority.The same idea is used to give priority to the one with the minimum number of pipeline stages required for the calculation.

The selection control of the next switching circuit 12 is performed when there is a maximum of four cases of conflicting outputs of the results of the addition/subtraction circuit system.

It is used to decide which one to give priority to, and if there is no particular result that you want to output quickly, the priority is given to the one in the later stages of the pipeline. For example, if there is a result in the last-stage isoline register 6, it must be given priority and transferred to the arithmetic register 16, otherwise the result will be lost, so it should be given top priority. Below, using the same idea, higher priority is given to the later stages. In addition, if there is something that you want to output the result quickly in 1%2, for example, if an instruction that uses the result as an operand is waiting for execution, immediately store the result in the calculation register 16,
If it is not read and executed, performance will deteriorate, so
Even if another result remains in the pipeline register on the downstream side without being transferred to the arithmetic register 16, control is performed to overtake this result and store it in the arithmetic register 16 as far as possible. . The switching circuit 13 is also similar to the switching circuit 12.

Fritsuno flop 101~107.201~207.3
01 to 307 are multiplication circuit systems, respectively.

Each pipeline stage of the addition/subtraction circuit system and the logic operation circuit system represents a valid bit, that is, a valid flag, which indicates the presence of valid data.The details of this and the control circuit 15 are shown in FIG. It has become.

FIG. 2 mainly focuses on the addition/subtraction circuit 2 and describes the details thereof. When OR land is given to the adder/subtracter circuit 2, as the operation progresses in the Yaipline style, the flip-flop 20
1, 202, and 203 become 11 in order, and at the same time as the calculation result is obtained, the flip roller f204 becomes 1''.If the result obtained at this time can be transferred to the calculation register 16, the transfer will be performed. flip flop 2
04 becomes %l"→@0", flip-flop 205
ends without becoming 1. If there is a conflict with another and the priority is low and cannot be transferred, the result is put into the pipeline register 4 and at the same time the flip 70 knob 204 is set to 11".
→"0", flip-flop 205 is '0m-4"l"
No, the result is not transferred to the calculation register 16? Indicates that the data has moved to register 4 for Eveline. Below are the Tsukuibline registers 5, 6° flip flora f206,
The same applies to 207.

The storage address registers 221 to 226 are registers that rotate the storage address when storing the result of addition and subtraction in the calculation register 16. Land address register 23
1.232 is a register that holds the 2 Oz operation register address of the instruction that is about to start operation.

When waiting for the result of an instruction currently being executed, it continues to be held in this register regardless of execution.

The contents of the land address registers 231 and 232 are compared with the storage address registers 226, 225, and 224, and if there is a match, the match signals 1601, 1602, and 1603 become "1#" for each blank stage. .Priority change signal 1701.170 from these signals
2 is made. NoJ? corresponding to valid bits 201-207? If the Eveline stages are called A-G, this logical table is as follows.

If you want the result in the E stage to be faster than the result in the front F stage, set the signal 1701 that suppresses the valid bit of the F stage to 0'', so that the result in the white stage is faster than the result in the E stage. E if you want
The logic is such that the signal 1702 for suppressing the effective playback of the stage is set to '0#.

The switching circuit 12 is controlled by flip-flops f204 to 207 that change the valid bits and priority change signals 1701 and 1.
702, signal 14021'l instructing that the result of the addition/subtraction circuit system can be output with priority: Therefore, this is done.

First, if the priority change signals 1701 and 1702 are both "1" and there is no priority change, if the signal 1402 is "1#", the flip-flop 207.
206, 205, and 204. For example, if the first flip-flop with 1" is 206, then in order to transfer the result of the corresponding pipeline register 5 to the operation register 16, AND'l'-) 217-2
140, the output signal 1206 of the corresponding palm gate 216
becomes 11", and the switching circuit 12
Zostar 5 will be selected and the results will be transferred.

If the signal 1402 is "0", the result of the addition/subtraction circuit system cannot be transferred to the arithmetic register 16, so AND) r'" - whichever output from 217 to 214 (1207 to 1204)
Also, the signals 1306 to 1304 are all "O".
1'', the contents of the 7 flip-flops 204-206 are transferred as they are to the flip-flops 205-207.

Next, if we consider the case where there is a priority change, 5, for example, 2 of the flip-flops 207, 206, 205°204
06 and 205 are "1", and storage address register 2
26 contents and operand address registers 231.23
2 does not match (signal 1601="O"), and the contents of storage address register 225 and operand address register 231iu232 match (signal 1602="1").
”), the instruction that is about to be executed next is waiting for the operation result in the E stage, and the result of the E stage is given priority over the result of the F stage and stored in the operation register 16. In this case, the priority change signal 1701=-"O= suppresses the output signal of the 7-lip float 206, the output signal of the AND gate 216 becomes "O", and the AND dart 215 The output signal of -'1# becomes 2. Switching circuit 1
In step 2, the register 4 for the noise line is selected, and the results in the F stage and the results in the E stage are transferred.

In this case, the results on the F stage that have been overtaken and not transferred are transferred to the G stage.

Next, selection control of the switching circuit 14 will be explained.

Signals 1501 and 1502 indicating that there is at least one result to be transferred from each arithmetic circuit system to the arithmetic register 16.
．． 1503 are the outputs of the flip-flop 107,
These are the logical sum of the outputs of flip-flops 204 to 207 and the logical sum of the outputs of flip-flops 302 to 307.

Input these three signals, prioritize the multiplier circuit system,
Follow the order of addition/subtraction circuit system and logical operation system.

A signal 1401 for selecting the output of the multiplication circuit system, a signal 1402 for selecting the output of the addition/subtraction circuit system. A signal 1403 that returns all the outputs of the logic operation system is generated, and selection control of the switching circuit 14 is performed using this signal.

FIG. 3 is an instruction sequence for explaining an example of speeding up when results are not waited. ■The command means performance. O-
The same applies to O.

FIG. 4-A shows the conventional device in the instruction sequence of FIG.
It is a time chart of instruction execution when there is no switching circuit 12 or 13. Instruction execution starts once per machine cycle
If an instruction can only be executed in the order of the given instruction sequence, ■~
■About the command? il machine cycle offset multiplication circuit 1, addition/subtraction circuit 2. The addition/subtraction circuit 2 is instructed to perform calculations, and the calculation results are obtained in the 7th cycle, the 4th cycle, and the 4th cycle, respectively, so the writing to the calculation register 16 is completed.
In 3, results are obtained for the instructions of ■■■.

In this case, there is no problem even if the resulting instructions change. However, assuming that the instruction (3) is started to be executed at timing 4 (dotted line in FIG. 4-A).

Since this is an addition/subtraction, the result is found at timing 7 after four machine cycles, which coincides with the timing at which the result of the instruction (2) is found, causing a problem. Therefore, this can be avoided by delaying the start of execution of the instruction (■) by one machine cycle and having it executed from timing 5 (solid line in Figure 4-A).
. The same applies to the instruction (2). Executing seven instructions in this way requires a total of 16 machine cycles.

FIG. 4-B is a time chart of the apparatus of the present invention in the instruction sequence of FIG. 3, ie, in FIG. 1. In this case, for all the instructions from ■ to ■, unlike the conventional case described above, there is no need to worry about conflicts in operation results.

Start execution with a one-machine cycle delay. timing 6
The results of the instructions ■ and ■ conflict, but according to the priority order,
The result of the instruction (2) is selected by the switching circuit 12-14 and transferred to the arithmetic register 16.

The result of the instruction (2) is not transferred to the operation register 16 but is transferred to the pipeline register 7. Next, timing 7
In this case, the results of the instructions ■, ■, ■, and ■ conflict with each other, but the result of the instruction ■ is selected by the switching circuit 14 and transferred to the arithmetic register 16 according to the priority order. The result of the instruction (2) is moved to the line register 4, and the results of the instructions (2) and (2) are moved to the pipeline registers 8 and 7, respectively. Next, at timing 8, the results of the instructions ■, ■, and ■ conflict, but the result of the instruction ■ is transferred from the pipeline register 4 to the arithmetic register 16 through the switching circuit 12.14 in accordance with the priority order. The results of the instructions (2) and (2) are transferred to pipeline registers 9 and 8, respectively. Next, at timing 9, the results of the instructions ■ and ■ compete with each other, but the result of the instruction ■ is transferred from the line register 9 to the arithmetic register 16 through the switching circuits 13 and 14 in accordance with the priority j. The result of the instruction (2) is used for the pipeline and is disclosed to Nosta 9. At timing 1o, the result of the instruction (3) is transferred from the pipeline register 9 to the operation register 16 through the switching circuits 13 and 14 without any conflict. The result of the instruction (①) is stored without conflict at timing 13, and as a result, it only takes 13 machine cycles to execute 7 instructions.
It will be understood that the speed will be increased.

Furthermore, the reason why the lengths of the lines are the same is that if the lengths of the lines and lines are all the same, then the input for each machine cycle will always have an output for each machine cycle without contention. This is because the result can be obtained from any output of the pipeline register for transfer.The reason why the result is simply taken from the arbitrary output of the pipeline register for transfer is that the calculation register is updated as soon as possible unless there is a conflict, and this This is because if there is an instruction that uses the result as an oiland in a subsequent instruction, it can be executed quickly.

FIG. 5 is a sequence of instructions for explaining an example of waiting for results. Since the description method is the same as that in FIG. 3, the explanation will be omitted.

FIG. 6-A is a time chart for the instruction sequence in FIG. 5 assuming that there is no priority change circuit. The instructions ①, ②, ① are sequentially executed at timings 9, 10, .
At step 11, the results are transferred. The instruction (2) starts execution at timing 13 only after the result of the instruction (2) is calculated, transferred to the ZOSTER 16, and read out (timing 12). In contrast, the priority change circuit in the device of the present invention [9] As shown in the time chart of Fig. 6-B,
The results of the instructions ■, ■, and ■ are transferred because the address match signal 1603 of the D stage is busy for 11 m at timing 9.■
, ■, ■ are executed in this order, and the execution of the instruction (■) starts at timing 11, so that it can be understood that speeding up is achieved.

〔Effect of the invention〕

As explained above, in an information processing device having a plurality of pipelined arithmetic units with different functions, when the minimum number of twig line stages required for each operation is different, the following stage for each arithmetic unit is provided. By adding the necessary number of pipeline registers that simply transfer results to the system, the number of stages in each calculation system pipeline can be made equal, and the calculation result can be output from any of the added pipeline registers. If you try to select one of the full outputs and there is a conflict between the outputs of the two arithmetic units and the outputs of the added pipeline registers in the same arithmetic unit, you may need the result quickly. If there is something to do, give priority to this, otherwise give priority to the output from the later stage of the /'P e-line register, which has the effect of reducing the required machine cycles and speeding up the operation. .

Ru.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing a part of FIG. 1 in full detail, and FIG. FIG. 5 is an example of an instruction sequence for explaining the present invention in detail. 4-A, 4-B, 6-A, and 6-B are time charts for explaining the present invention in detail. Explanation of symbols: 1...multiplication circuit, 2...addition/subtraction circuit. 3...Logic operation circuit, 4-11...Shizostar for Noquizo line, 12-14...Switching circuit, 15...Control circuit. 7:7/'), 214-21' I-AND circuit,
721-223...Result address register, 224
~226...Storage address register, 231, 232
-...Eiland address register, 241...-Comparator, 1001゜1002...Operand supply node,
1003...Result storage path, 1204-1207...
- Selection signal in selection circuit 12, 1401 to 1403
... Selection signal in selection circuit 14, 1501...
1503...Control signal indicating that there is a result to be stored in each calculation system. 1601-1603...Land address match signal for result address/piece. 1701.1702...Priority change signal. Fan 3 figure OR3-1'? １ Figure 5■ R+03- RIOI X R+02■ R106
-R+04XR+Q5 ■ R109-R+07 10RI08 ■ RI+2 - RIIC1+RIIl■ Shaku 1+
5 ←RI+30 shaku114 Figure 6-B

Claims (1)

[Claims] 1. In an information processing device that has multiple pipelined arithmetic units with different functions, if the minimum number of pipeline stages required for each operation is different, it is possible to simply transfer the results for each arithmetic unit to the subsequent stage. a switching means that adds a necessary number of pipeline registers to perform the above processing so that the number of stages of each calculation system pipeline is equal, and outputs a calculation result from any of the added pipeline registers; If you try to select one of all result outputs and there is a conflict between the arithmetic unit output of the same arithmetic unit and the added pipeline register output, if there is one that requires the result quickly, select it. 1. An information processing device comprising: control means for giving priority to output from a later stage of a pipeline register.