JPS63223923A - Program counter circuit - Google Patents

Abstract

PURPOSE:To decrease the number of dynamic steps of a program containing many repeated processings by providing one more more registers which can prescribe a return address from a subroutine. CONSTITUTION:A stack 102 stores a first return address from a subroutine, and a register 103 stores a second return address from the subroutine. An instruction fetching means 108 fetches an instruction stored in an address designated by a program counter 101. When an instruction decoded by a decoder 9 is a subroutine call instruction, the contents of a counter 101 are pushed to the stack 102, and a call destination address if transferred to the counter 101. Also, when said instruction is a return 1 instruction, the contents of the stack 102 are popped to the counter 101, and when said instruction is a return 2 instruction, the contents of the stack 102 are popped, but the contents of the register 103 are transferred to the counter 101. In such a way, by one instruction, a return and an unconditional jump can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program counter circuit for determining a return address from a subroutine in a microprocessor.

[Conventional technology]

Generally, when performing a certain set of processing within one information processing program, it is widely used to make that part a subroutine for ease of program design and understanding. For example, data is divided into clusters A, B, and others, and as shown in FIG. 4, it is necessary to process subroutine 1 for data belonging to cluster A, and process subroutine 2 for data belonging to cluster B. Consider a process in which this process is repeated until the data no longer belongs to cluster A or cluster B. In this case, the collective process A
, B can be made into subroutines, making it easier to design and understand. Such a processing program in a microprocessor having a conventional program counter circuit will be described. FIG. 3 is a block diagram of main parts of a conventional program counter circuit. As shown in FIG. 3, the conventional program counter circuit includes a program counter 301 for specifying the address of the next instruction to be executed;
It is composed of a stack 302 for storing a return address from a subroutine and a stack pointer 303. When a subroutine call instruction is executed, the contents of program counter 301 are pushed onto stack 302. That is, the stack pointer 303 is incremented by 1, and the contents of the program counter 301 are saved to the stack 302. Furthermore, when a return instruction is executed, the return address saved in the stack 302 is popped into the program counter 301. That is, the stack 302
The contents of are transferred to the program counter 301, the stack pointer 303 is decremented by 1, and the stack 302 is returned to the state before the subroutine call. Here, a case where the above-mentioned processing is executed by a microprocessor having a conventional program counter circuit will be described. The program in this case is as follows.

(1) Enter data.

(2) If condition 1 is false, (5) jump.

(3) Call subroutine 1.

(4) Jump to (1).

(5) If clause #2 is false, jump to (8).

(6) Call subroutine 2.

(7) Jump to (1).

(8) Finished.

Note that the condition 1 is that the data belongs to cluster A.

Condition 2 assumes that the data belongs to cluster B.

At this time, subroutine 1 is as follows.

(11) Execute process A.

(12) Return.

Similarly, subroutine 2 is as follows.

(21) Execute process B.

(22) Return.

As mentioned above, if condition 1 or condition 2 is true, then (1
) will be executed.

[Problem that the invention seeks to solve]

When the above processing is executed by a microprocessor with a conventional program counter circuit, it is necessary to execute an unconditional jump instruction for repeat processing after executing an unconditional jump to the return address using a return instruction in a subroutine. The disadvantage is that the jump to (+) must be performed in two instructions.

In the conventional program counter circuit described above, when executing a subroutine call by repeated processing, the jump must be performed twice for each repetition, whereas the program counter circuit of the present invention uses By providing one or more registers that can specify a return address from a subroutine, this method has an original content that provides a similar function with only a return instruction.

[Means for solving problems]

The program counter circuit of the present invention includes a program counter, a stack circuit that holds the contents of the program counter when a subroutine is called, one or more registers that store a return address from the subroutine, and the stack circuit according to the type of return instruction. and a selection control circuit that selects either the output of the register or the output of the register and inputs the selected output to the program counter.

[Example 1] The present invention will be explained by examples.

FIG. 1 is a block diagram of a program counter circuit in one embodiment of the present invention. In FIG. 1, 101 is a program counter, 102 is a stack for storing the first return address from the subroutine, 103 is a register for storing the second return address from the subroutine, and 104 is the output of the stack 102. or register 103
105 is a stack pointer, 106 is a control circuit for controlling the multiplexer 104, 107 is a memory for storing a program, 108 is an instruction fetch means for fetching instructions from the memory 107, 109 is the instruction fetch means 108
This is an instruction decoder for decoding instructions read from.

The operation of a microprocessor having a program counter circuit according to the present invention when calling a subroutine will be described. In the microprocessor having the program counter circuit of the present invention, any return address from a subroutine can be set in register 103 in advance. The program counter 101 specifies the address of the next instruction to be executed in the program stored in the memory 107. The instruction fetch means 108 fetches the instruction stored at the address specified by the program counter 101, and the instruction decoder 109 decodes the fetched instruction. If the decoded instruction is a subroutine call instruction, the contents of the program counter 101 are pushed onto the stack 102, and the call destination address is written to the program counter 101. Transfer to. Furthermore, if the decoded instruction is a return 1 instruction, the contents of the stack 102 are popped into the program counter 101, and if the decoded instruction is a return 2 instruction, the contents of the stack 102 are popped into the program counter 101.
The control circuit 106 pops the contents of register 103 but does not transfer them to program counter 101, but transfers the contents of register 103 to program counter 101.

Here, a program counter circuit according to the present invention is included.

A case will be described in which the processing shown in FIG. 4 is executed by a microprocessor. The program in this case is as follows.

(1) Set the address (2) in the register 103.

(2) Enter data.

(3) If condition 1 is false, jump to (5).

(4) Call subroutine 1.

(5) If condition 2 is false, jump to (7).

(6) Call subroutine 2.

(7) Finished.

Note that condition 1: data belongs to cluster A.

Condition 2: Data shall belong to cluster B.

At this time, subroutine 1 is as follows.

(11) Execute process A.

(12) Return 2° Similarly, subroutine 2 is as follows.

(21) Execute process B.

(22) Return 2゜As mentioned above, the address (2) is set in register 103 in (1), so when the return 2 instruction of subroutine 1 and subroutine 2 is executed, it will jump to (2). Become. As a result, return 2 simultaneously functions as a return command from a subroutine and an unconditional jump command for repeated processing, thereby realizing the processing shown in FIG. 4.

Also, when executing return 2, the stack pointer 105 operates in the same way as when executing return 1, so the stack is returned to the state before the subroutine call. As described above, in this embodiment, a return instruction and an unconditional jump instruction can be executed in one instruction.

[Example 2] FIG. 2 is a block diagram of a second embodiment of the invention.

In the figure, 201 is a program counter, 202 is a stack for storing the first return address from the subroutine, 203-1 is a register for storing the second return address from the subroutine, and 203-2 is a register for storing the second return address from the subroutine. Tamu's register, 20, which stores the third return address of
4 is a multiplexer that selects the output of the stack 202 or the register 203-1 or the register 203-2;
05 is the stack pointer, 206 is the multiplexer 20
207 is a memory for storing a program, 208 is an instruction fetch means for fetching instructions from the memory 207, and 209 is an instruction for decoding the instruction read from the instruction fetch means 208. It is a decoder.

The control circuit 206 in this embodiment pops the stack 202 and returns it to the program counter 201 for the return-1 instruction, and similarly pops the stack 202 for the return-2 instruction.
02, but the contents of register 203-1 are transferred to the program counter 201 without being transferred to the program counter, and the return 3 instruction also pops the stack 202, but the contents of register 203-2 are transferred to the program counter 201. The data is controlled to be transferred to the counter 201.

In this embodiment, by using registers that can specify the second and third return addresses from a subroutine, it is possible to provide multiple return addresses, and a return instruction and an unconditional jump instruction are used as one instruction. This can be achieved with

〔Effect of the invention〕

As explained above, by providing one or more registers that can specify the return address from a subroutine, the present invention makes it possible to execute a return and an unconditional jump with a single instruction. This has the effect of greatly reducing the number of target steps and the program execution time.

[Brief explanation of drawings]

1 is a block diagram showing the configuration of the program counter circuit in Embodiment 1 of the present invention, FIG. 2 is a block diagram showing the configuration of the program counter circuit in Embodiment 2 of the present invention, and FIG. 4 is a block diagram showing the configuration of a conventional program counter circuit, and FIG. 4 is a flow chart showing an example of repetitive processing. 101.201,301...Program counter, 1
02.202,302...Stack, 103,203
-1,203-2...Register, 104,204...
・Multiplexer, 105, 205, 303... Stack pointer, 106.206... Control circuit, 107
．． 207...Memory, 108,208...Instruction fetch means, 109,209...Instruction decoder. Agent Patent Attorney Susumu Uchihara Pa' ・-, ++. /θ7 1st surface 2θ7 $ 2 M Kaya 4WJ

Claims (1)

[Claims] A program counter circuit of a microprocessor includes a program counter, a stack circuit that holds the contents of the program counter when a subroutine is called, one or more registers that store a return address from the subroutine, and the stack circuit according to the type of return instruction. and a selection control circuit that selects either the output of the register or the output of the register and inputs the selected output to the program counter.