JPH03281523A - Dm monitoring-circuit - Google Patents

Abstract

PURPOSE:To obtain the title circuit capable of monitoring total bits by each unit, having an address coincidence detecting part of output value of a sequential counter and monitoring address counter, stationary monitoring address setting part, address coincidence detecting part thereof and output value selecting part. CONSTITUTION:Total bits in DM are monitored by bit unit by a DM monitoring- circuit having an address coincidence detecting part 4A of an output value of a sequential counter 1 and a monitoring address counter 2, a stationary monitoring address setting part 3 indicating empty bit line of data bit line as a pattern inserting bit line for monitoring, a second address coincidence detecting part 4B of detecting coincidence of output value of the sequential counter 1 and the stationary monitoring address setting part and a selection part 5 of selecting one of output values of the sequential counter 1, the monitoring address counter 2 and the stationary monitoring address setting part 3 by the outputs values of the first and the second address coincidence detecting parts 4A and 4B.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a DM (Direct Memory) monitoring circuit, and particularly to a DM (Direct Memory) monitoring circuit for monitoring line setting memory failures.
Regarding monitoring circuits.

[Conventional technology]

Conventionally, this type of DM monitoring circuit has performed monitoring by adding one parity bit to the input data bit string and checking the parity of the target data bit string and the parity bit that is simultaneously output when the data bit string is output from the memory. .

[Problem to be solved by the invention]

The conventional DM monitoring circuit described above performs monitoring by adding one bit of odd or even parity to an input data bit string and checking the parity bit added to the output data bit string of the same memory. Therefore, although it is possible to detect errors in several opposite bits of the input/output data bit string, there is a drawback that it is impossible to detect errors in even numbers of bits.

[Means to solve the problem]

The DM monitoring circuit of the present invention includes a first address coincidence detection section that detects coincidence of output values with a sequential counter and a monitoring address counter, and a fixed monitoring address setting that specifies an empty bit string of a data bit string as a monitoring pattern insertion bit string. a second address coincidence detection section that detects coincidence between the output values of the sequential counter and the fixed monitoring address setting section; and a selection section that selects an output value of any one of the monitoring address counter and the fixed monitoring address setting section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, a sequential counter 1 is an address counter for writing a data bit string to the DM, and counts up every time this sequential counter 1 completes one cycle. The address match detection section 4A detects a match between the output values of the sequential counter 1 and the monitoring address counter 2. On the other hand, the address match detection section 4B detects the match between the output values of the sequential counter 1 and the monitoring address counter 2. On the other hand, the address match detection section 4B detects a match between the output values of the sequential counter 1 and the monitoring address counter 2. A match between the output values of the fixed monitoring address setting section 3, which designates a bit string as a monitoring pattern insertion bit string, and the sequential address counter 1, which designates the address of the frame, is detected. The selection unit 5 selects the output value of the fixed monitoring address setting unit 3 when a match is detected by the address match detection unit 4B, and selects the output value of the fixed monitoring address setting unit 3 when a match is detected by the address match detection unit 4A. address counter 2
If address matching is not detected in either case, the output value of sequential counter 1 is selected as is. At this time, the data input operation to M is normally a sequential write operation depending on the output value of the sequential counter l, but the data input operation to the monitoring address counter 2
As a result, the monitoring pattern is inserted sequentially from the first data bit string of the frame, and the data of the bit string monitored by the monitoring address counter 2 is set by the fixed monitoring address setting section 3 under the control of the address match detection section 4B. Since the monitoring pattern and the data bit string are exchanged, the monitoring pattern can be sequentially inserted into all the data bit strings of the frame input to the DM, and the DM monitoring is executed.

〔Effect of the invention〕

As explained above, the present invention includes a fixed monitoring address setting section that specifies a monitoring insertion bit string in an empty bit string, so that a monitoring pattern can be sequentially inserted into all data bit strings constituted by a frame. This has the effect of allowing all bits in the DM to be monitored bit by bit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a data format showing a data bit string of this embodiment. l...Sequential counter, 2...Monitoring address counter, 3...Fixed monitoring address setting section, 4A. 4B... Address match detection section, 5... Selection section.

Claims (1)

[Claims] a first address coincidence detection section that detects coincidence of output values with the sequential counter and the monitoring address counter; a fixed monitoring address setting section that specifies an empty bit string of the data bit string as a monitoring pattern insertion bit string; A second address coincidence detection section detects coincidence of the output values of the fixed monitoring address setting section, and the output values of the first and second address coincidence detection sections are used to detect the sequential counter, the monitoring address counter, and the fixed monitoring address. 1. A DM monitoring circuit comprising: a selection section for selecting an output value of any one of the address setting sections.