JPH06324952A - Patrol control circuit for memory device - Google Patents

Abstract

PURPOSE:To prevent system down from occurring by switching a patrol operation for a first area and a patrol operation for a second area so as to alternately perform those operations at a certain period. CONSTITUTION:When the prescribed patrol operation is finished for all the addresses S0-S1 of a first area 6, an address counter 3 starts outputting the address of the second area 7 in a memory part 5. When the patrol operation for addresses S1-S2 of the second area 7 is finished, the counter 3 stops outputting, a selector 14 selects the output signal of an address counter 2 again and the patrol operation of the first area 6 is performed. Such an operation is repeated, and the first area 6 and the second area 7 are alternately patrolled up to addresses Sn-1-Sn of the second area 7. Thus, since the first area 6 is frequently patrolled, saving of one-bit error can be efficiently performed concerning the entire memory part 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a patrol control circuit of a memory device, and more particularly to a patrol address generating function thereof.

[0002]

2. Description of the Related Art A conventional patrol control circuit of a memory device has only one address counter, and a patrol address is generated by the one address counter to make it uniform for all addresses in the memory section. Patrol is performed, and when there is a correctable error, the correction and rewriting are performed.

However, the memory section of the memory device is
An area where data is first written, such as an area for storing data used by the OS, and thereafter, only a read operation is frequently performed and a write operation is rarely performed, and a normal write / read operation. Generally, it is used by dividing into a region where a write operation and a read operation are always performed, such as a region where a write operation is performed.

When a 1-bit error due to a soft error occurs, normal data is directly written in the latter area by the next write command, or data is rewritten in accordance with the patrol operation. Although the relief is made, the former area retains erroneous data until the data is rewritten due to the patrol operation because the number of write commands is very small. Usually, in a large-sized memory device, it takes several tens of hours until the patrol for all addresses in the memory section is completed, so there is a high probability that it will overlap with another 1-bit error in the former area. The patrol control circuit of 1 performs patrol at the same frequency for the above-mentioned two types of areas.

[0005]

As described above, in the patrol control circuit of the conventional memory device, when the 1-bit error due to the soft error occurs in the area where the write command is very small, the data re-creation accompanying the patrol operation is performed. Since erroneous data is held for a long time until writing is performed, there is a high probability of overlapping with another 1-bit error, which causes a system down due to an uncorrectable error.

[0006]

A patrol control circuit for a memory device according to the present invention outputs a patrol address for each of a first area having a small number of write commands and a second area having a large number of write commands in a memory section. First and second address counters, a first select signal for switching the patrol addresses from the first and second address counters at a constant cycle during patrol operation, the patrol address, and an address during normal operation And a selector for inputting the first select signal and selecting one of the two types of patrol addresses.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, the patrol control circuit 1 is
Address counters 2 and 3, and timing control circuit 4
And a selector 14, and patrols the memory unit 5 at a constant cycle.

The address counter 2 has a first area 6 (S ₀ -S ₀₎ which is an area in which the number of write commands of the memory section 5 is very small.
Determine the patrol address for ₁ ). Address counter 4 determines the patrol address for the second region 7 is a region for normal write / read operation of the memory unit 5 (S ₁ ~S _n).

The timing control circuit 4 has a first select signal 15 for switching the patrol addresses output from the address counters 2 and 3 at a constant cycle, and the patrol address (address) 10 from the selector 14.
And a second select signal 18 for switching the address 16 in the normal operation.

The selector 14 inputs the patrol address output from the address counters 2 and 3, and selects one of them by the select signal 15.

The 1-bit error detection / correction circuit 9 inputs the read data 11 read from the memory section 5, detects and corrects the 1-bit error, and sends the corrected data 12 to the check bit generation circuit 8.

The check bit generation circuit 8 adds a check bit to the corrected data 12 and sends it to the memory section 5 as a write data 13.

The selector 19 inputs the address 10 from the selector 14 and the address 16 in the normal operation,
Either one of them is selected by the select signal 18 and sent to the memory unit 5 as the address 17.

Next, the operation of the patrol control circuit configured as described above will be described.

When the patrol operation is started by the patrol control circuit 1, first, the address counter 2 sequentially outputs the addresses S _{0 to} S ₁ of the first area 6 of the memory section 5,
The selector 14 selects it by the select signal 15 from the timing control circuit 4 and outputs it as the address 10. This address 10 is input to the selector 19,
It is selected by the select signal 18 from the timing control circuit 4 and sent to the memory section 5 as the address 17.

The memory section 5 reads the data stored in the area designated by the address 17 and sends it as read data 11 to the 1-bit error detection / correction circuit 9.

The 1-bit error detection / correction circuit 9 detects whether or not the read data 11 has a 1-bit error,
If there is a 1-bit error, it is corrected and sent as corrected data 12 to the check bit generation circuit 8.

The check bit generation circuit 8 adds a check bit to the input correction data 12 and sends it as write data 13 to the memory section 5.

The memory section 5 rewrites the write data 13 in the area of the original address.

When the above patrol operation is completed for all the addresses S _{0 to} S _{1 of} the first area 6, the address counter 3 starts outputting the addresses of the second area 7 of the memory section 5.

The selector 14 selects the output signal of the address counter 3 by the select signal 15 from the timing control circuit 4 and outputs it as the address 10.

The above patrol operation is performed up to the address S _{2 in} the second area 7 by the above procedure.

[0025] patrol operation for the address S ₁ to S ₂ of the second region 7 is completed, the address counter 3 stops the output, the selector 14, the address counter 2 again
The output signal of is selected and the patrol operation of the first area 6 is performed.

When the patrol operation of the first area 6 is completed, the address counter 3 is moved to the second area 7 of the memory section 5.
The output of the addresses S _{2 to} S ₃ is started and the area between them is patrolled.

By repeating the above operation, the first area 6 and the second area 7 are alternately patrold from the addresses S _{n-1 to} S _n of the second area 7. As a result, the first area 6 is frequently patrolled, so that the 1-bit error can be efficiently relieved for the entire memory unit 5.

[0028]

As described above, the patrol control circuit of the memory device according to the present invention includes the memory section of the memory device.
It is divided into a first area in which mainly a read operation is frequently performed and a write operation is rarely performed, and a second area in which both a write operation and a read operation are always performed, and a patrol operation and a second area for the first area are performed. By switching so that the patrol operation for the area is alternately performed at a fixed cycle,
This has the effect that the patrol operation for the first area can be performed frequently. Therefore, a 1-bit error due to a soft error in the first area can be remedied at an early point, so that it cannot be corrected together with other 1-bit errors. This has an effect of preventing an error and causing a system down.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 Patrol control circuit 2.3 Address counter 4 Timing control circuit 5 Memory section 6 First area 7 Second area 8 Check bit generation circuit 9 1-bit error detection / correction circuit 10 Patrol address (address) 11 Read data 12 Corrected data 13 Write Data 14 ・ 19 Selector 15 ・ 18 Select signal 16 ・ 17 Address

Claims (1)

[Claims] 1. A first and second address counter for outputting a patrol address of each of a first area having a small number of write commands and a second area having a large number of write commands in a memory section, and the first counter during a patrol operation. And timing control for outputting a first select signal for switching the patrol address from the second address counter at a constant cycle and a second select signal for switching the patrol address and the address during normal operation. A patrol control circuit for a memory device, comprising: a circuit; and a selector for inputting the first select signal to select one of two types of patrol addresses.