JPH03263364A - 半導体集積装置 - Google Patents

半導体集積装置

Info

Publication number
JPH03263364A
JPH03263364A JP2062953A JP6295390A JPH03263364A JP H03263364 A JPH03263364 A JP H03263364A JP 2062953 A JP2062953 A JP 2062953A JP 6295390 A JP6295390 A JP 6295390A JP H03263364 A JPH03263364 A JP H03263364A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
integrated circuit
signal
sealed
signal pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2062953A
Other languages
English (en)
Inventor
Takashi Senba
仙波　隆司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2062953A priority Critical patent/JPH03263364A/ja
Publication of JPH03263364A publication Critical patent/JPH03263364A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積装置に関し、特に複数の素子を同一
基板上に搭載する半導体集積装置に関する。
〔従来の技術〕
従来、この種の半導体集積装置は、基板全体を封止する
もの、及び、半導体集積回路部のみを樹脂等によりコー
ティングするものがある。
第２図に半導体集積回路を含む複数の素子が搭載される
基板全体を封止する従来例の縦断面図を、又、第３図に
基板上の半導体集積回路のみを樹脂等によりコーティン
グあるいはボッティングする従来例の縦断面図を示す。
〔発明が解決しようとする課題〕
上述した従来の基板全体を封止する半導体集積装置は、
封止工程が最後となり、封止工程以前に半導体集積回路
に対する汚染については未対策のままとなり品質上好ま
しくなく、又、半導体集積回路以外の複数の素子の交換
といった追加工程に対しては処置出来ないという欠点が
ある。
又、第３図に示す基板上の半導体集積回路のみを樹脂６
で封止する半導体集積装置は、気密性に劣り、耐湿性が
劣る欠点がある。又、樹脂の比誘電率によっては、信号
線のカップリグ等、電気的特性上高周波特性を劣化させ
る欠点をも有している。
〔課題を解決するための手段〕
本発明の半導体集積装置は、多層基板上に半導体集積回
路を含む複数の素子を搭載する半導体集積装置において
、前記半導体集積回路の信号をワイヤにより前記多層基
板上に設置された信号パッドと接続し、前記半導体集積
面路に電気接続すべき前記素子と前記信号パッドとを貫
通孔を介し前記多層基板の内層に設けられた配線パター
ンにて接続し、前記半導体集積回路、前記ワイヤ及び前
記信号パッドを一体容器にて封止する構造である。
前記一体容器を導体で形成し接地してもよい。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図は本発明の一実施例の縦断面図である。
１は多層基板を示し、本例では内層を１層とした例を示
す。２は半導体集積回路、即ち、チップを示す。３は多
層基板１と半導体集積回路２との信号線を接続するボン
ディングワイヤを示す。４は半導体集積回路２と同一基
板上に搭載される素子、５は一体容器、７は多層基板１
の内層中に設けられた信号線、８は多層基板１中の上層
と内層信号線７とを接続するピアホール、９は上層部配
線、１０は信号パッドを示す。半導体集積回路２は多層
基板上に搭載され、その信号線はボンディングワイヤ３
により−たん多層基板１上の信号パッド１０に接続され
、そのままピアホール８にて内層信号線７に接続される
。内層信号線７はもう一方のピアホール８を介して上層
部配線９及び半導体集積回路２以外の素子４等に接続さ
れる。
又、半導体集積回路２．ボンディングワイヤ３゜信号パ
ッド１０は一体容器５により封止される。
一体容器５を金属性にして接地するようにすれば、シー
ルド効果が得られるので、高周波信号を扱う場合等に効
果がある。
〔発明の効果〕
以上説明したように本発明は、多層基板上に半導体集積
回路を含む複数の素子を搭載する半導体集積装置におい
て、半導体集積回路の信号とワイヤにより基板上に設置
された信号パッドを接続し、半導体集積回路と電気接続
すべき素子と信号パッドとをピアホールを介し内層に設
けられた配線パターンにて接属し、半導体集積回路、ワ
イヤ及び信号パッドを一体容器にて封止する構造をとる
ことにより、封止する工程以降の半導体集積回路の汚染
等の被害を防ぐことが可能となるばかりでなく、半導体
集積回路以外の複数の素子の交換といった追加工程に対
しても半導体集積回路の被害を抑えることが可能となる
。又、樹脂封止と異なり容器による封止方法をとること
から気密性に優れ、耐湿性の問題も皆無になる効果があ
る。合わせで、高周波特性確保の意味においても、一体
容器を金属製にして接地することにより、優れたシール
ド効果を得ることもできる。
【図面の簡単な説明】
第１図は本発明の一実施例の縦断面図、第２図及び第３
図は２つの従来例のそれぞれの縦断面図である。 １・・・多層基板、２・・・半導体集積回路、３・・・
ボンディングワイヤ、４・・・素子、５・・・一体容器
、６・・・樹脂、７・・・内層信号線、８・・・ピアホ
ール、９・・・上層部配線、１０・・・信号パッド。

Claims (2)

    【特許請求の範囲】
  1. １．多層基板上に半導体集積回路を含む複数の素子を搭
    載する半導体集積装置において、前記半導体集積回路の
    信号をワイヤにより前記多層基板上に設置された信号パ
    ッドと接続し、前記半導体集積回路に電気接続すべき前
    記素子と前記信号パッドとを貫通孔を介し前記多層基板
    の内層に設けられた配線パターンにて接続し、前記半導
    体集積回路、前記ワイヤ及び前記信号パッドを一体容器
    にて封止する構造を特徴とする半導体集積装置。
  2. ２．前記一体容器を導体で形成し接地したことを特徴と
    する請求項１記載の半導体集積装置。
JP2062953A 1990-03-13 1990-03-13 半導体集積装置 Pending JPH03263364A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2062953A JPH03263364A (ja) 1990-03-13 1990-03-13 半導体集積装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2062953A JPH03263364A (ja) 1990-03-13 1990-03-13 半導体集積装置

Publications (1)

Publication Number Publication Date
JPH03263364A true JPH03263364A (ja) 1991-11-22

Family

ID=13215197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2062953A Pending JPH03263364A (ja) 1990-03-13 1990-03-13 半導体集積装置

Country Status (1)

Country Link
JP (1) JPH03263364A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1729340A1 (en) * 2004-03-26 2006-12-06 Mitsubishi Denki Kabushiki Kaisha High frequency package, transmitting and receiving module and wireless equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1729340A1 (en) * 2004-03-26 2006-12-06 Mitsubishi Denki Kabushiki Kaisha High frequency package, transmitting and receiving module and wireless equipment
EP1729340A4 (en) * 2004-03-26 2010-10-20 Mitsubishi Electric Corp HIGH FREQUENCY PACKAGE, TRANSMITTING AND RECEIVING MODULE AND WIRELESS EQUIPMENT

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