JPH03248454A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH03248454A JPH03248454A JP2046109A JP4610990A JPH03248454A JP H03248454 A JPH03248454 A JP H03248454A JP 2046109 A JP2046109 A JP 2046109A JP 4610990 A JP4610990 A JP 4610990A JP H03248454 A JPH03248454 A JP H03248454A
- Authority
- JP
- Japan
- Prior art keywords
- island
- substrate
- inner leads
- pins
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 abstract description 15
- 229920005989 resin Polymers 0.000 abstract description 15
- 238000007789 sealing Methods 0.000 abstract description 10
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Structure Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、混成集積回路装置、特にリードフレーム方式
の樹脂封止装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and particularly to a lead frame type resin sealing device.
〔従来の技術］
従来の、この種の混成集積回路装置は、第５図に示すよ
うなリードフレーム（平面図）を用い、部品搭載、ワイ
ヤボンディング後、樹脂封止をしてからフレームカット
をして製作される。図において、１′はリードフレーム
で、７′はアイランドである。このアイランド７′はそ
の４隅部および各辺の中央をそれぞれ第１吊りピン２′
、第２吊りピン１３’によってリードフレーム１′に支
持されている。アイランド７′にほぼ同寸法の絶縁性基
板４′を固着してから、第６図に示すように受動素子８
′、能動素子９′を基板４′の回路パターン１１’に融
着し、各部品間、およびインナーリード５’ 、６’と
の間を金属細線１０’により接続する。次に、外装樹脂
３′で封止し、リードフレーム１′を切断して完成する
。第６図は第５図のＣＣ′線の断面図である。[Prior Art] Conventionally, this type of hybrid integrated circuit device uses a lead frame (plan view) as shown in Fig. 5, and after mounting components and wire bonding, resin sealing is performed, and then frame cutting is performed. It is manufactured by In the figure, 1' is a lead frame and 7' is an island. This island 7' has its four corners and the center of each side connected to first hanging pins 2'.
, is supported by the lead frame 1' by a second hanging pin 13'. After fixing an insulating substrate 4' of approximately the same size to the island 7', a passive element 8 is attached as shown in FIG.
', the active element 9' is fused to the circuit pattern 11' of the substrate 4', and connections are made between each component and between the inner leads 5' and 6' using thin metal wires 10'. Next, it is sealed with an exterior resin 3' and the lead frame 1' is cut to complete the process. FIG. 6 is a sectional view taken along line CC' in FIG.
［発明が解決しようとする課題］
混成集積回路装置は、基板の寸法が大きくなるので、半
導体装置のように、アイランドをその４隅部の吊りピン
で支えるだけでは、樹脂封止の際樹脂流入速度によりア
イランドが変形する。そこで、上述のようにアイランド
の辺中央にも吊りピンを設けている。しかし、次に説明
するように、この辺中央の吊りピンを設けることは、イ
ンナーリードの各ピン間の寸法が大きくなり、多ピン化
のｒ重書になっている。[Problems to be Solved by the Invention] Hybrid integrated circuit devices have large substrates, so if the island is only supported by hanging pins at its four corners like a semiconductor device, resin inflow during resin encapsulation cannot be achieved. The island deforms depending on the speed. Therefore, as mentioned above, a hanging pin is also provided at the center of the side of the island. However, as will be explained next, providing the hanging pin at the center of this side increases the size between each pin of the inner lead, resulting in an r-fold layout with a large number of pins.
リードフレームの加工方法としてエツチング法とプレス
法と２種類の手段があるが、いずれの方法でも加工可能
な最小ピン間寸法はリードフレーム板厚に０．８を乗じ
た数値より小さくできない。従って、例えばリードフレ
ームの板厚を０．１５ｍｍとした場合、加工可能最小ピ
ン間寸法は０１２ｍｍとなり、リード幅を ０．４ｍｍ
とした場合、リードピッチ寸法は０．５２１１１Ｑ＋と
なる。更にリード間に吊りピンを設けた場合のり−ドピ
ッチは、リード幅０．４ｍｍに加工可能最小ピン間寸法
２ Ｘ Ｏ，１２ｍｎ＋と吊りピンの加工可能最小ピン
寸法０．１２ｍｍを加えて、０．７６ｍｍになる。There are two methods of processing a lead frame: an etching method and a pressing method, but in either method, the minimum distance between pins that can be processed cannot be made smaller than the value obtained by multiplying the lead frame board thickness by 0.8. Therefore, for example, if the thickness of the lead frame is 0.15 mm, the minimum pin-to-pin dimension that can be processed is 0.12 mm, and the lead width is 0.4 mm.
In this case, the lead pitch dimension is 0.52111Q+. Furthermore, when suspending pins are provided between the leads, the gluing pitch is 0.4mm by adding the minimum machinable pin-to-pin dimension of 2 x O, 12mm+ and the machinable minimum pin dimension of the suspending pin of 0.12mm to the lead width of 0.4mm. It becomes 76mm.
以上説明したように、アイランド辺中央に吊りピンを余
分に設けると、リードピッチは０、７６ｍｍとなり、狭
ピツチ指向に対し、１．４６倍不利となり、多ピン化が
不可能になる。As explained above, if an extra hanging pin is provided at the center of the island side, the lead pitch becomes 0.76 mm, which is 1.46 times disadvantageous compared to narrow pitch orientation, making it impossible to increase the number of pins.
本発明の目的は、上記の事情に鑑み、アイランドの吊り
ピン数は最小限に、すなわちアイランドの４隅部にとど
めるが、アイランドの変形が防止されるような構造にし
ている混成集積回路装置を提供することにある。In view of the above circumstances, an object of the present invention is to provide a hybrid integrated circuit device in which the number of hanging pins on the island is kept to a minimum, that is, at the four corners of the island, but the deformation of the island is prevented. It is about providing.
本発明の混成集積回路装置は、リードフレームから吊り
ピンで支持されるアイランドおよびインナーリードのす
べてもしくはその一部の先端部に、またがって絶縁性基
板を固着して樹脂封止されている。In the hybrid integrated circuit device of the present invention, an insulating substrate is fixed and resin-sealed across the tips of all or some of the islands and inner leads supported by hanging pins from the lead frame.
基板がアイランドだけでなく、インナーリードのすべで
あるいはその一部に固着されている。したがって、基板
の大部分を搭載するアイランドは、基板を介してインナ
ーリードによっても支持されているので、樹脂封止の際
に樹脂流入速度による変形が生じない。吊りピンとして
は、装置の外形寸法に影響を与えないように４隅部に設
けるのみでよく、多ピン化に有利になる。The substrate is fixed not only to the island but also to all or part of the inner lead. Therefore, since the island on which most of the substrate is mounted is also supported by the inner leads through the substrate, deformation due to the resin inflow speed does not occur during resin sealing. The hanging pins need only be provided at the four corners so as not to affect the external dimensions of the device, which is advantageous for increasing the number of pins.
［実施例〕 以下、図面を参照して本発明の実施例につき説明する。[Example〕 Embodiments of the present invention will be described below with reference to the drawings.
第１図は第１の実施例に用いられるリードフレーム平面
図、第２図は樹脂封止後の第１図のＡＡ’線に相応する
装置断面図である。リードフレーム１はアイランド７を
吊るため吊りピン２を４隅に設け、更にアイランド７の
外周部にインナーリード５，６を配置し、このインナー
リード５，６の先端部とアイランド７全体に対し、回路
基板４を固着させる。この場合、回路基板４の固着はイ
ンナーリードのすべてでなくてもよい。この回路基板４
に受動素子８、能動素子９等を搭載し、金属細線１０等
を用いて接続し、外装樹脂３で封止する。FIG. 1 is a plan view of a lead frame used in the first embodiment, and FIG. 2 is a cross-sectional view of the device taken along line AA' in FIG. 1 after resin sealing. The lead frame 1 has hanging pins 2 at the four corners to hang the island 7, and inner leads 5 and 6 are arranged around the outer periphery of the island 7. Fix the circuit board 4. In this case, the circuit board 4 does not need to be fixed to all of the inner leads. This circuit board 4
A passive element 8, an active element 9, etc. are mounted on the board, connected using thin metal wires 10, etc., and sealed with an exterior resin 3.
次に第２の実施例につき説明する。第３図はリードフレ
ーム平面図、第４図は第３図のＢＢ′線に相応する装置
断面図である。この例では、アイランド７の周縁内部に
インナーリード６の先端が入るように、インナーリード
６の長さを長くし、またアイランド７の周縁に切欠部を
つくる。このインナーリード６の先端部とアイランド７
全体に対し、回路基板４を固着させる。この回路基板４
上に受動素子８、能動素子９等を搭載し、金属細線１０
等を用いて接続し外装樹脂３にて封止する。Next, a second embodiment will be explained. FIG. 3 is a plan view of the lead frame, and FIG. 4 is a sectional view of the device taken along line BB' in FIG. In this example, the length of the inner lead 6 is increased so that the tip of the inner lead 6 can fit inside the periphery of the island 7, and a notch is formed on the periphery of the island 7. The tip of this inner lead 6 and the island 7
The circuit board 4 is fixed to the whole. This circuit board 4
A passive element 8, an active element 9, etc. are mounted on the top, and a thin metal wire 10 is mounted.
etc., and sealed with exterior resin 3.
〔発明の効果］
以上説明したように、本発明はすべてのインナーリード
またはその一部の先端部とアイランド全体を回路基板に
固着させる構造を取ることにより、インナーリードがア
イランドの吊りピンを兼ねることになるため、アイラン
ドの各辺の中央に吊りピンを設ける必要がな（，４隅部
のみに設けるだけでよい。従って、加工可能最小リード
ピッチ寸法は、リードフレームの板厚を０．１５ｍｍ、
リード幅を０．４ｍｍとした場合、リードピッチは
０．５２ｍｍとなり、従来例の第５図の場合よりも小さ
くできる。有効外部リード数Ｃ各辺当り）は従来例の４
０本に対し４４本となり高機能化すなわち多ピンパッケ
ージ化に対し非常に効果がある。[Effects of the Invention] As explained above, the present invention has a structure in which the tips of all the inner leads or a part thereof and the entire island are fixed to the circuit board, so that the inner leads can also serve as suspension pins for the island. Therefore, there is no need to provide hanging pins at the center of each side of the island (they only need to be provided at the four corners. Therefore, the minimum lead pitch dimension that can be processed is the lead frame plate thickness of 0.15 mm,
When the lead width is 0.4 mm, the lead pitch is 0.52 mm, which is smaller than the conventional example shown in FIG. 5. The number of effective external leads (C per side) is 4 in the conventional example.
The number is 44 compared to 0, which is very effective for higher functionality, ie, multi-pin packaging.
第１図は本発明の第１実施例のリードフレーム平面図、
第２図は封止後の装置のＡＡ’線断面図、第３図は第２
実施例のリードフレーム平面図、第４図は封止後の装置
のＢＢ’線断面図、第５図は従来技術のリードフレーム
平面図、第６図は封止後の装置のＣＣ′線断面図である
。
■、１′・・・リードフレーム、
２．２′・・−吊りピン、 ３，３′・・−外装樹脂、
４．４′・・・回路基鈑、
５．５′・・−インナーリード、
６．６′・−・インナーリード、
７．７′・・・アイランド、８，８′・・−受動素子、
９．９′・・・能動素子、 １０．１０’・・−金属細
線、１．１．１１’・・・回路パターン、
１２、１２’・・・有効外部リード、
１３、１３’ −・−吊りピン。FIG. 1 is a plan view of a lead frame according to a first embodiment of the present invention;
Figure 2 is a sectional view taken along line AA' of the device after sealing, and Figure 3 is a cross-sectional view of the device after sealing.
A plan view of the lead frame of the embodiment, FIG. 4 is a sectional view taken along line BB' of the device after sealing, FIG. 5 is a plan view of the lead frame of the prior art, and FIG. 6 is a cross section taken along line CC' of the device after sealing. It is a diagram. ■, 1'...Lead frame, 2.2'...-hanging pin, 3,3'...-exterior resin,
4.4'...Circuit board, 5.5'...-Inner lead, 6.6'...-Inner lead, 7.7'...Island, 8,8'...-Passive element,
9.9'...Active element, 10.10'...-Thin metal wire, 1.1.11'...Circuit pattern, 12,12'...Effective external lead, 13,13'-- hanging pin.
Claims (1)
において、リードフレームから吊りピンで支持されるア
イランドおよびインナーリードのすべてもしくはその一
部の先端部に、またがって前記基板を固着して樹脂封止
してあることを特徴とする混成集積回路装置。In a hybrid integrated circuit device in which various components are mounted on an insulating substrate, the substrate is fixed and resin-sealed across the tips of all or some of the islands and inner leads supported by hanging pins from the lead frame. A hybrid integrated circuit device characterized in that the hybrid integrated circuit device is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2046109A JP2890621B2 (en) | 1990-02-26 | 1990-02-26 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2046109A JP2890621B2 (en) | 1990-02-26 | 1990-02-26 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03248454A true JPH03248454A (en) | 1991-11-06 |
| JP2890621B2 JP2890621B2 (en) | 1999-05-17 |
Family
ID=12737826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2046109A Expired - Fee Related JP2890621B2 (en) | 1990-02-26 | 1990-02-26 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2890621B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013141026A (en) * | 2005-03-07 | 2013-07-18 | Agere Systems Inc | Integrated circuit package |
| CN104952856A (en) * | 2015-06-27 | 2015-09-30 | 华东光电集成器件研究所 | Integrated circuit capable of realizing double-sided assembly |
| EP3055880A1 (en) * | 2013-10-11 | 2016-08-17 | MediaTek Inc. | Semiconductor package |
| US10163767B2 (en) | 2013-10-11 | 2018-12-25 | Mediatek Inc. | Semiconductor package |
-
1990
- 1990-02-26 JP JP2046109A patent/JP2890621B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013141026A (en) * | 2005-03-07 | 2013-07-18 | Agere Systems Inc | Integrated circuit package |
| EP3055880A1 (en) * | 2013-10-11 | 2016-08-17 | MediaTek Inc. | Semiconductor package |
| EP3055880A4 (en) * | 2013-10-11 | 2017-11-08 | MediaTek Inc. | Semiconductor package |
| US10163767B2 (en) | 2013-10-11 | 2018-12-25 | Mediatek Inc. | Semiconductor package |
| CN104952856A (en) * | 2015-06-27 | 2015-09-30 | 华东光电集成器件研究所 | Integrated circuit capable of realizing double-sided assembly |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2890621B2 (en) | 1999-05-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |