JPH03180055A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03180055A JPH03180055A JP31952089A JP31952089A JPH03180055A JP H03180055 A JPH03180055 A JP H03180055A JP 31952089 A JP31952089 A JP 31952089A JP 31952089 A JP31952089 A JP 31952089A JP H03180055 A JPH03180055 A JP H03180055A
- Authority
- JP
- Japan
- Prior art keywords
- outer leads
- semiconductor element
- semiconductor device
- lead
- packaging base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims description 7
- 238000004806 packaging method and process Methods 0.000 abstract description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 238000005452 bending Methods 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000003566 sealing material Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体素子を厚膜基板又はプリント基板等
に搭載してなる半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a semiconductor element is mounted on a thick film substrate, a printed circuit board, or the like.
第５図、第６図、第７図は従来の半導体装置を示すもの
である０図において、１はリードフレームのダイパッド
部２ａ上に接着剤３にて固定されている半導体チップ、
４はこの半導体チップ１の表面に形成された電極とリー
ドフレームのインナリード部２ｂを電気的に配線してい
る金属細線であり、これら半導体チップ１と金属細線４
は外力からの保護のため封止材５で覆われ、半導体素子
を形成している。２ｃはリードフレームのアウタリード
部で、基板７に形成された電極パッド部７ａに半田６に
て固定されている。5, 6, and 7 show conventional semiconductor devices. In FIG. 0, 1 is a semiconductor chip fixed on a die pad portion 2a of a lead frame with an adhesive 3;
Reference numeral 4 denotes a thin metal wire that electrically connects the electrode formed on the surface of the semiconductor chip 1 and the inner lead portion 2b of the lead frame.
is covered with a sealing material 5 for protection from external forces, forming a semiconductor element. Reference numeral 2c denotes an outer lead portion of the lead frame, which is fixed to an electrode pad portion 7a formed on the substrate 7 with solder 6.
次に動作について説明する。半導体チップ１は、リード
フレームに形成されたダイボンドパッド部２ａに接着剤
３にて固定され、その表面に形成された配線電極とリー
ドフレームに形成されたインナリード２ｂを金属配線４
にて電気的に配線し、さらに外力からの保護のため封止
材５にてパッケージされ、半導体素子が形成されている
。さらにこの半導体素子の機能を引き出すアウタリード
２ｃは前記半導体のパッケージ面に対して外方向に向っ
ており、搭載基板７の表面に形成した電極パッド７ａに
半田６により接続されている。Next, the operation will be explained. The semiconductor chip 1 is fixed to a die bond pad part 2a formed on a lead frame with an adhesive 3, and the wiring electrode formed on the surface thereof and the inner lead 2b formed on the lead frame are connected to a metal wiring 4.
A semiconductor element is formed by electrically wiring the semiconductor element and packaging it with a sealing material 5 for protection from external forces. Further, an outer lead 2c that brings out the functions of this semiconductor element faces outward with respect to the package surface of the semiconductor, and is connected to an electrode pad 7a formed on the surface of the mounting board 7 by solder 6.
従来の半導体装置は以上の様に構成されているので、半
導体素子アウタリードの数が増加した場合、第６図に示
すようにアウタリード間隔が広いため、半導体素子の外
形を大幅に拡大しなければならず、それに伴って実装基
板も大型化しなければならず、高密度化が困難であるな
ど問題点があった。Conventional semiconductor devices are configured as described above, so when the number of semiconductor element outer leads increases, the outer lead spacing is wide, as shown in Figure 6, so the external shape of the semiconductor element must be significantly enlarged. As a result, the size of the mounting board had to be increased, making it difficult to achieve high density.
この発明は以上のような問題点を解消するためになされ
たもので、半導体素子のアウタリードの間隔を最小限に
することによりアウタリードの数に対して半導体素子の
外形を小さくし、これに伴って実装基板への搭載面積が
小さくなり、高密度な半導体装置を得ることを目的とす
る。This invention has been made to solve the above-mentioned problems, and by minimizing the spacing between the outer leads of a semiconductor element, the outer size of the semiconductor element can be made smaller in relation to the number of outer leads. The purpose is to reduce the mounting area on a mounting board and to obtain a high-density semiconductor device.
この発明に係る半導体装置は、半導体素子のアウタリー
ドの板厚面を実装基板面に対してたてに平行に配置した
ものである。In the semiconductor device according to the present invention, the thickness surface of the outer lead of the semiconductor element is arranged vertically and parallel to the surface of the mounting board.
〔作用〕
この発明における半導体装置は、基板へ搭載される半導
体素子のアウタリードの板厚面を搭載基板面に対して平
行に配置することにより、アウタリードの間隔を小さく
することが可能となり、このためアウタリードが並ぶ方
向の外形寸法を大幅に縮小でき、実装基板の高密度化が
図れる。[Function] In the semiconductor device of the present invention, by arranging the thickness plane of the outer leads of the semiconductor element mounted on the substrate parallel to the surface of the mounting substrate, it is possible to reduce the interval between the outer leads. The external dimensions in the direction in which the outer leads are lined up can be significantly reduced, making it possible to increase the density of the mounting board.
以下、この発明の一実施例を図について説明する。第１
図において、１．２ａ、２ｂ、 ３ 、４ 、５は前記
従来例のものと同様であるが、リードフレームのアウタ
ーリード２ｄは中間の折り曲げポイント２ｅでインナー
リード２ｂに対して９０’回転して捩っているため、実
装基板７の表面に対してその板厚面が第２図のようにた
てに平行に配置され、前記実装基板７に形成した電極パ
ッド７ａに半田６にて半田付されている。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1.2a, 2b, 3, 4, and 5 are the same as those of the conventional example, but the outer lead 2d of the lead frame is rotated by 90' with respect to the inner lead 2b at the intermediate bending point 2e. Since it is twisted, its thickness surface is vertically arranged parallel to the surface of the mounting board 7 as shown in FIG. 2, and the electrode pad 7a formed on the mounting board 7 is soldered with solder 6. has been done.
以上の様にインナリード２ｂとアウタリード２ｄの中間
において折り曲げポイント２ｃを形成することにより、
アウタリード２ｄの板厚方向の面が実装基板７に形成さ
れた電極パッド７ａ面に平行に配置され、半田６により
接続される。By forming the bending point 2c between the inner lead 2b and the outer lead 2d as described above,
The surface of the outer lead 2d in the thickness direction is arranged parallel to the surface of the electrode pad 7a formed on the mounting board 7, and is connected with the solder 6.
ここで、リードフレームの板厚を０．１５、アウタリー
ド２ｄの間隔を０．２としても、リードピッチは０．３
５と小さくできる。これに対し従来のものでは、アウタ
リード２ｃの幅は０．４であり、アウターリード２ｃの
間隔を０．２としても、リードピッチは０．６は必要と
なる。従ってこれらを比較した場合、リードピッチで０
．２５の短縮が図れるため、半導体チップの大型化に伴
い、リード数が増加した場合の効果は大きい。Here, even if the thickness of the lead frame is 0.15 and the interval between the outer leads 2d is 0.2, the lead pitch is 0.3.
It can be made as small as 5. In contrast, in the conventional case, the width of the outer leads 2c is 0.4, and even if the interval between the outer leads 2c is 0.2, a lead pitch of 0.6 is required. Therefore, when comparing these, the lead pitch is 0.
．． Since the number of leads can be reduced by 25, the effect is great when the number of leads increases as semiconductor chips become larger.
なお前記実施例では、封止樹脂５の内部にインナリード
とアウタリードの折り曲げ部があるが、封止樹脂の外部
に形成してもよく、また前記実施例は１枚のリードフレ
ームを加工することによりインナリードとアウタリード
の方向を変えているが、２枚のリードフレームを組合せ
ることによっても同じ効果が得られる。In the above embodiment, the bent portions of the inner lead and the outer lead are inside the sealing resin 5, but they may be formed outside the sealing resin, and in the above embodiment, a single lead frame is processed. Although the directions of the inner lead and outer lead are changed by this method, the same effect can be obtained by combining two lead frames.
以上のようにこの発明によれば、半導体素子のアウタリ
ードの板厚面を実装基板面に平行に取り付ける様に構成
したため、実装密度の高い半導体装置が得られる効果が
ある。As described above, according to the present invention, since the thickness surface of the outer lead of the semiconductor element is attached parallel to the surface of the mounting board, it is possible to obtain a semiconductor device with high packaging density.
第１図は本発明による半導体装置の断面図、第２図、第
３図はその半導体素子の斜視図と側面図、第４図は実装
基板の斜視図、第５図は従来の半導体装置の断面図、第
６図、第７図はその半導体素子の斜視図と側面図である
。
図中、１は半導体チップ、２ａはグイパッド、２ｂはイ
ンナリード、２ｄはアウタリード、３は接着剤、４は金
属細線、５は封止材、６は半田、７は基板、７ａは電極
パッドである。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view of a semiconductor device according to the present invention, FIGS. 2 and 3 are a perspective view and a side view of the semiconductor element, FIG. 4 is a perspective view of a mounting board, and FIG. 5 is a diagram of a conventional semiconductor device. The sectional view, FIGS. 6 and 7 are a perspective view and a side view of the semiconductor element. In the figure, 1 is a semiconductor chip, 2a is a pad, 2b is an inner lead, 2d is an outer lead, 3 is an adhesive, 4 is a thin metal wire, 5 is a sealing material, 6 is a solder, 7 is a substrate, and 7a is an electrode pad. be. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ップと電気的に接続されるリードフレームのアウタリー
ドが基板に形成した電極パッドに接続される半導体装置
において、前記アウタリードの板厚面が前記基板表面上
にたてに平行に配列して取り付けられていることを特徴
とする半導体装置。In a semiconductor device in which a semiconductor chip is enclosed in a package and outer leads of a lead frame electrically connected to the semiconductor chip are connected to electrode pads formed on a substrate, the thickness side of the outer leads is on the surface of the substrate. A semiconductor device characterized by being mounted vertically and in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31952089A JPH03180055A (en) | 1989-12-08 | 1989-12-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31952089A JPH03180055A (en) | 1989-12-08 | 1989-12-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03180055A true JPH03180055A (en) | 1991-08-06 |
Family
ID=18111146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31952089A Pending JPH03180055A (en) | 1989-12-08 | 1989-12-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03180055A (en) |
-
1989
- 1989-12-08 JP JP31952089A patent/JPH03180055A/en active Pending
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