JP2513781B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2513781B2 JP2513781B2 JP63129591A JP12959188A JP2513781B2 JP 2513781 B2 JP2513781 B2 JP 2513781B2 JP 63129591 A JP63129591 A JP 63129591A JP 12959188 A JP12959188 A JP 12959188A JP 2513781 B2 JP2513781 B2 JP 2513781B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- semiconductor device
- frame
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Manufacturing Of Electrical Connectors (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 〔概 要〕 半導体パッケージに半導体チップを搭載し、配線を行
う組立方法を改良した半導体装置に関し、 容易に実施できる構造の変更により、大型化した半導
体チップを多くの工数を用いないで半導体パッケージに
組み付けることが可能な半導体装置の提供を目的とし、 周縁部にパッド部を備えた半導体チップと、枠の内側
の前記パッド部に対応する位置にメタライズ部を備えた
枠状のセラミック枠とを具備し、前記半導体チップを前
記セラミック枠の内側に嵌入し、前記パッド部とメタラ
イズ部とを、溶融した金属により融着するよう構成す
る。DETAILED DESCRIPTION [Overview] A semiconductor device having a semiconductor package mounted on a semiconductor package and having an improved assembly method for wiring is disclosed. For the purpose of providing a semiconductor device that can be assembled into a semiconductor package without using a semiconductor chip, a semiconductor chip having a pad portion on a peripheral portion and a frame having a metallized portion at a position corresponding to the pad portion inside the frame A ceramic frame, the semiconductor chip is fitted inside the ceramic frame, and the pad portion and the metallized portion are fused by a molten metal.
本発明は、半導体装置に係り、特に半導体パッケージ
に半導体チップを搭載し、配線を行う組立方法を改良し
た半導体装置に関するものである。The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor chip is mounted on a semiconductor package and a wiring method is improved.
近年、半導体チップのメモリー容量の増大やゲートア
レイ数の増大等の要求が半導体装置に対して高まってい
る。In recent years, demands for semiconductor devices such as an increase in memory capacity of semiconductor chips and an increase in the number of gate arrays are increasing.
このため半導体チップが大型化し、この大型化した半
導体チップを収納するためキャビティの大型化、或いは
リード数を増加するための多ピン化が半導体パッケージ
に対して必要になってきた。For this reason, the semiconductor chip becomes large, and it becomes necessary for the semiconductor package to have a large cavity for accommodating the large semiconductor chip, or to have a large number of pins for increasing the number of leads.
以上のような状況から大型の半導体チップを小型の半
導体パッケージに収納することが可能な半導体装置が要
望されている。Under the circumstances as described above, there is a demand for a semiconductor device capable of housing a large semiconductor chip in a small semiconductor package.
従来の半導体装置の構造を第６図〜第８図により説明
する。The structure of a conventional semiconductor device will be described with reference to FIGS.
第６図は従来の半導体パッケーを示す側断面図、第７
図は従来の半導体チップを示す平面図で、図示している
ように、表面にはパッド部13が周辺から少し離れた位置
に設けられており、第８図は組立が完了した半導体装置
の斜視図である。FIG. 6 is a side sectional view showing a conventional semiconductor package, and FIG.
The figure is a plan view showing a conventional semiconductor chip. As shown in the figure, a pad portion 13 is provided on the surface at a position slightly apart from the periphery. FIG. 8 is a perspective view of a semiconductor device after assembly. It is a figure.
従来のDITタイプの半導体装置は、第６図に示すよう
に両側に外リード16を備えたリードベース11のキャビテ
ィ11aに、第７図に示す半導体チップ12を金シリコン等
の共晶合金により融着し、内リード17と第７図に示す半
導体チップ12のパッド部13とを金，アルミニウム，銅等
の配線14により接続し、キャップ15を金シリコン等の共
晶合金或いはハンダ，ガラス等の封止材18にて融着して
固定する第８図（ａ）に示すような構造を有している。In a conventional DIT type semiconductor device, a semiconductor chip 12 shown in FIG. 7 is melted with a eutectic alloy such as gold silicon in a cavity 11a of a lead base 11 having outer leads 16 on both sides as shown in FIG. Then, the inner lead 17 and the pad portion 13 of the semiconductor chip 12 shown in FIG. 7 are connected by a wiring 14 of gold, aluminum, copper or the like, and the cap 15 is made of a eutectic alloy such as gold silicon or solder, glass or the like. It has a structure as shown in FIG. 8 (a) in which it is fused and fixed by the sealing material 18.
従来の半導体装置には上記のDITタイプの他に、第８
図（ｂ）に示すLCCタイプや第８図（ｃ）に示すFPTタイ
プがある。In addition to the above DIT type, conventional semiconductor devices include
There are the LCC type shown in FIG. 8B and the FPT type shown in FIG. 8C.
半導体装置の機能を向上させるために、半導体チップ
12が大型化すると、それに伴い半導体パッケージが大き
くなり、大型の半導体パッケージの半導体装置はプリン
ト板への実装に際しては所要面積が増大し、このプリン
ト板を用いる装置が大型になっている。Semiconductor chips to improve the function of semiconductor devices
As the size of 12 increases, the size of the semiconductor package increases accordingly, and the area required for mounting the semiconductor device of the large-sized semiconductor package on a printed board increases, and the device using this printed board becomes large.
また、多ピン化に伴い必要数のリードを限られた大き
さの半導体パッケージに設けなければならないので、リ
ードの間隔が狭くなる傾向がある。Further, as the number of leads increases, it is necessary to provide a required number of leads in a semiconductor package having a limited size, so that the lead interval tends to become narrow.
以上説明の従来の半導体装置においては、半導体チッ
プの大型化に伴って多ピン化し、必要数のリードを限ら
れた大きさの半導体パッケージに設けなければならない
ので、リードの間隔が狭くなっている。このためアルミ
ニウム配線等のワイヤボンディングに多大の工数を必要
とし、また、リードの間隔が狭くなっているので、ワイ
ヤの曲がりやワイヤ相互の接触障害が発生するという問
題点があり、また、半導体チップが大型化し、半導体パ
ッケージとの融着面積が増大するため、金シリコン等の
共晶で融着する際に半導体チップや半導体パッケージに
クラックが生じるという問題点があった。In the conventional semiconductor device described above, the number of pins is increased as the size of the semiconductor chip is increased, and a required number of leads must be provided in a semiconductor package of a limited size, so the lead interval is narrowed. . For this reason, a large number of man-hours are required for wire bonding of aluminum wiring, etc. Further, since the lead interval is narrow, there is a problem that bending of the wires and contact failure between the wires occur, and the semiconductor chip However, there is a problem that cracks are generated in the semiconductor chip and the semiconductor package when they are fused with a eutectic such as gold silicon because they are large in size and the fusion area with the semiconductor package increases.
本発明は以上のような状況から容易に実施できる構造
の変更により、大型化した半導体チップを多くの工数を
用いないで半導体パッケージに組み付けることが可能な
半導体装置の提供を目的としたものである。The present invention has an object to provide a semiconductor device capable of mounting a large-sized semiconductor chip in a semiconductor package without using many man-hours by changing the structure that can be easily implemented from the above situation. .
上記問題点は、周縁部にパッド部を備えた半導体チッ
プと、枠の内側の前記パッド部に対応する位置にメタラ
イズ部を備えた枠状のセラミック枠とを具備し、前記半
導体チップを前記セラミック枠の内側に嵌入し、前記パ
ッド部とメタライズ部とを、溶融した金属により融着し
た本発明による半導体装置によって解決される。The above problems include a semiconductor chip having a pad portion on a peripheral portion and a frame-shaped ceramic frame having a metallized portion at a position corresponding to the pad portion inside a frame, wherein the semiconductor chip is a ceramic chip. This is solved by the semiconductor device according to the present invention, which is fitted inside the frame, and the pad portion and the metallized portion are fused by a molten metal.
即ち本発明においては、半導体チップのパッド部に対
応する位置の枠の内側に、メタライズ部を備えた枠状の
セラミック枠の内側に、半導体チップを嵌入し、半導体
チップの周縁部に設けたパッド部とセラミック枠のメタ
ライズ部とを対峙させ、このパッド部とメタライズ部と
を溶融した金属により融着するので、半導体チップが半
導体パッケージに融着されていないから、半導体チップ
や半導体パッケージにクラックが発生せず、ワイヤによ
り半導体チップと半導体パッケージとを接続していない
のでワイヤボンディングに工数を必要とせず、ワイヤの
曲がりやワイヤ相互の接触障害も発生しない。That is, in the present invention, the semiconductor chip is fitted inside the frame at the position corresponding to the pad portion of the semiconductor chip, inside the frame-shaped ceramic frame provided with the metallized portion, and the pad provided on the peripheral portion of the semiconductor chip is provided. Section and the metallized portion of the ceramic frame face each other, and since the pad portion and the metallized portion are fused by the molten metal, since the semiconductor chip is not fused to the semiconductor package, the semiconductor chip or the semiconductor package is cracked. Since it does not occur and the semiconductor chip and the semiconductor package are not connected by the wire, no man-hours are required for wire bonding, and bending of the wire and contact failure between the wires do not occur.
以下第１図〜第５図について本発明の三種の実施例を
説明する。Three types of embodiments of the present invention will be described below with reference to FIGS.
第１図は半導体パッケージを示す斜視図、第２図は半
導体チップを示す平面図、第３図は第１の実施例の半導
体装置を示す側断面図、第４図は第２の実施例の半導体
装置を示す斜視図、第５図は第３の実施例の半導体装置
を示す側断面図である。1 is a perspective view showing a semiconductor package, FIG. 2 is a plan view showing a semiconductor chip, FIG. 3 is a side sectional view showing a semiconductor device of a first embodiment, and FIG. 4 is a view of a second embodiment. FIG. 5 is a perspective view showing a semiconductor device, and FIG. 5 is a side sectional view showing a semiconductor device according to a third embodiment.
第２図に示す半導体チップ２の表面のパッド部３は半
導体チップ２の周縁部に設けられており、従来の半導体
チップのように半導体チップの周辺との間に隙間が設け
られていない。The pad portion 3 on the surface of the semiconductor chip 2 shown in FIG. 2 is provided in the peripheral portion of the semiconductor chip 2, and no gap is provided between the pad portion 3 and the periphery of the semiconductor chip unlike the conventional semiconductor chip.
第１図はメタライズ部４を枠の内側に備えたセラミッ
ク枠１の斜視図であり、このメタライズ部４はこの枠の
内側に嵌入する第２図に示す半導体チップ２のパッド部
３に対応した位置に設けられている。FIG. 1 is a perspective view of a ceramic frame 1 having a metallized portion 4 inside the frame. The metallized portion 4 corresponds to the pad portion 3 of the semiconductor chip 2 shown in FIG. It is provided in the position.
第３図に示す第１の実施例は、このセラミック枠１の
内側に半導体チップ２を嵌入し、半導体チップ２のパッ
ド部３とセラミック枠１のメタライズ部４とを対峙さ
せ、この部分をハンダ等で融着して固定したものであ
る。In the first embodiment shown in FIG. 3, the semiconductor chip 2 is fitted inside the ceramic frame 1, the pad portion 3 of the semiconductor chip 2 and the metallized portion 4 of the ceramic frame 1 are opposed to each other, and this portion is soldered. It is fixed by fusing with, for example.
その後セラミック枠１の枠内にポリイミド或いはレジ
ン等の樹脂をセラミック枠１の表面に出ないようにドロ
ッピングし、セラミック枠１と半導体チップ２とを固定
する。Thereafter, a resin such as polyimide or resin is dropped into the ceramic frame 1 so as not to appear on the surface of the ceramic frame 1, and the ceramic frame 1 and the semiconductor chip 2 are fixed.
DRAM等のメモリーチップにおいてポリイミドを用いる
と、α線が照射されても誤動作しないようにする効果も
ある。The use of polyimide in memory chips such as DRAMs also has the effect of preventing malfunction even when irradiated with α rays.
このようなセラミック枠１と半導体チップ２とを用い
て半導体装置を製造すると、ワイヤボンディングを行う
ことが必要でないので、電気的接続工数が激減し、ワイ
ヤの曲がりやワイヤ相互の接触障害も発生しない。When a semiconductor device is manufactured using such a ceramic frame 1 and a semiconductor chip 2, it is not necessary to perform wire bonding, so the number of electrical connection steps is drastically reduced, and bending of wires and contact failure between wires do not occur. .
また、半導体チップ２を融着しないのでクラックの発
生も防止可能となり、半導体チップ２の背面が露出して
いるので、放熱も良くなる。Further, since the semiconductor chip 2 is not fused, the generation of cracks can be prevented, and the rear surface of the semiconductor chip 2 is exposed, so that heat dissipation is also improved.
第４図に示す第２の実施例では、42アロイ等の合金よ
りなる外部リード６をメタライズ部４にロー付けするの
で、外部との接続を取ることが可能となる。In the second embodiment shown in FIG. 4, the external lead 6 made of an alloy such as 42 alloy is brazed to the metallized portion 4, so that external connection can be established.
第５図に示す第３の実施例では、第５図（ａ）に示す
ようにメタライズ部４をセラミック枠１の外側に延長し
て設けるので、LCCタイプの半導体パッケージとして用
いることが可能であり、第５図（ｂ）に示すようにこの
メタライズ部４に外部リード６をロー付けすると、DIT
タイプの半導体パッケージとして用いることも可能であ
る。In the third embodiment shown in FIG. 5, since the metallized portion 4 is provided outside the ceramic frame 1 as shown in FIG. 5 (a), it can be used as an LCC type semiconductor package. When the external lead 6 is brazed to the metallized portion 4 as shown in FIG.
It can also be used as a type of semiconductor package.
以上の説明から明らかなように本発明によれば極めて
簡単な構造の半導体パッケージと半導体チップとを用い
て半導体装置を組み立てることが可能となるので、半導
体パッケージをリード間隔の狭い小型化したものとする
ことができ、電気的接続工数は激減し、ワイヤの曲がり
やワイヤ相互の接触障害も発生しないので、組立工程の
コストダウンが可能になり、また、半導体チップの背面
が露出しているので、放熱効率が高くなる等の利点があ
り、著しい経済的及び、信頼性向上の効果が期待でき工
業的には極めて有用なものである。As is clear from the above description, according to the present invention, it is possible to assemble a semiconductor device using a semiconductor package and a semiconductor chip having an extremely simple structure. Since the number of electrical connection steps is drastically reduced, and wire bending and contact failure between wires do not occur, the cost of the assembly process can be reduced, and since the back surface of the semiconductor chip is exposed, It has advantages such as high heat dissipation efficiency, and can be expected to have remarkable economic and reliability improving effects, which is extremely useful industrially.
第１図は本発明による一実施例の半導体パッケージを示
す斜視図、 第２図は本発明による一実施例の半導体チップを示す平
面図、 第３図は本発明による第１の実施例の半導体装置を示す
側断面図、 第４図は本発明による第２の実施例の半導体装置を示す
斜視図、 第５図は本発明による第３の実施例の半導体装置を示す
側断面図、 第６図は従来のパッケージを示す側断面図、 第７図は従来の半導体チップを示す平面図、 第８図は従来の半導体装置を示す斜視図、 である。 図において、 １はセラミック枠、 ２は半導体チップ、 ３はパッド部、 ４はメタライズ部、 ５は樹脂部、 ６は外部リード、 を示す。1 is a perspective view showing a semiconductor package of an embodiment according to the present invention, FIG. 2 is a plan view showing a semiconductor chip of an embodiment of the present invention, and FIG. 3 is a semiconductor of a first embodiment of the present invention. FIG. 4 is a side sectional view showing a device, FIG. 4 is a perspective view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 5 is a side sectional view showing a semiconductor device according to a third embodiment of the present invention. FIG. 7 is a side sectional view showing a conventional package, FIG. 7 is a plan view showing a conventional semiconductor chip, and FIG. 8 is a perspective view showing a conventional semiconductor device. In the figure, 1 is a ceramic frame, 2 is a semiconductor chip, 3 is a pad part, 4 is a metallized part, 5 is a resin part, and 6 is an external lead.
Claims (1)
ップ（２）と、 枠の内側の前記パッド部（３）に対応する位置にメタラ
イズ部（４）を備えた枠状のセラミック枠（１）とを具
備し、 前記半導体チップ（２）を前記セラミック枠（１）の内
側に嵌入し、前記パッド部（３）とメタライズ部（４）
とを、溶融した金属により融着したことを特徴とする半
導体装置。1. A frame-shaped ceramic having a semiconductor chip (2) having a pad portion (3) on a peripheral portion and a metallized portion (4) at a position corresponding to the pad portion (3) inside the frame. A frame (1), the semiconductor chip (2) is fitted inside the ceramic frame (1), the pad portion (3) and the metallized portion (4)
A semiconductor device in which and are fused by a molten metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63129591A JP2513781B2 (en) | 1988-05-26 | 1988-05-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63129591A JP2513781B2 (en) | 1988-05-26 | 1988-05-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01298732A JPH01298732A (en) | 1989-12-01 |
| JP2513781B2 true JP2513781B2 (en) | 1996-07-03 |
Family
ID=15013232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63129591A Expired - Fee Related JP2513781B2 (en) | 1988-05-26 | 1988-05-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2513781B2 (en) |
-
1988
- 1988-05-26 JP JP63129591A patent/JP2513781B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01298732A (en) | 1989-12-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |