JPH03245270A - Setting system for logic simulation environment - Google Patents

Abstract

PURPOSE:To facilitate highly accurate verification by setting the logical signal/ driving timing with the action description and simultaneously with production of a logic verification program source. CONSTITUTION:A data input part 103 converts a logic verification test instruction inputted via a keyboard 101 of a TSS terminal and the pseudo RAM initial data and the action description obtained at execution of the test instruction into each prescribed format and stores these formats in a source code master file 107. A source code analyzing part 106 reads out a source code and gives a logic verification test instruction train part to a compiler 104 to start it. A compiled load module is set to a pseudo memory 109 via a loader 105. At the same time, a pseudo RAM data part is set to a pseudo RAM of a logic simulation processor 110 via the loader 105. A logic description part is registered in an action description file 108. Then the processor 110 is started by the loader 105 when all setting operations are through.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for setting logic signals and signal values in logic simulation, and particularly to a method for setting a logic simulation environment for simulating the logic operation of a large-scale logic circuit.

[Prior art]

Conventionally, logic simulations have been performed by running a logic verification program in order to confirm that computer logic to be simulated operates normally.

Such a logic verification program sets various logic operating environments at the software command level.

Note that this type of device is disclosed in Japanese Patent Application Laid-Open No. 1-266676.
As described in the above publication, there is a logic simulation device that performs logic simulation processing using a behavioral description language that describes state changes of logic signals.

[Problem to be solved by the invention]

In the above conventional technology, the creation of the source code of the logic verification program, the creation of the executable format module, and the creation of the behavioral description for operating the logic simulation execution environment are performed separately and are managed in different formats. There is a problem that not only is the program complicated, but also that it is difficult to ensure consistency between the program and the behavioral description when executing a logic simulation.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a logic simulation environment setting method that simultaneously creates a logic verification program and a behavioral description and centrally manages them as source code.

[Means to solve the problem]

In order to achieve the above object, the present invention provides means for inputting a test instruction string, initial setting conditions, and a behavior description section, means for compiling the test instruction string, and inputting the test instruction string and the initial setting conditions. The method includes means for loading the behavioral description section into a pseudo memory and executing a logical simulation, and means for delivering the behavioral description section to a logical simulation processing device.

[For production]

According to the above-mentioned means, when creating a logic verification program,
Since a logical simulation environment that is difficult or impossible to set using software can be set using a behavioral description language, highly accurate verification is easily possible.

〔Example〕

An embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of a logic simulation environment setting method according to the present invention. In FIG. 19, the host computer 102 includes a data input section 103, a compiler 104, a loader 105, and a source code analysis section 106, and further includes a TSS terminal 101, a source code mask file 107, and a behavior description. A file 108, a pseudo memory 109, and a logic simulation processing device 110 are connected.

-3= The data input unit 103 converts the logic verification test instruction sequence, pseudo RA, M initial data (registers, memory) and operational description during execution of the test instruction sequence input from the keyboard of the TSS terminal 101 into a predetermined format. It is converted and stored in the source code mask file 107.

The source code analysis unit 106 reads the source code, passes the logic verification test instruction string portion to the compiler, and starts the compiler 104. The compiled load module is stored in the pseudo memory 109 via the loader 105.
is set to Further, the pseudo RAM data portion such as register data is directly set to the pseudo RAM on the logic simulation processing device 110 side via the loader 105. The behavioral description portion is registered in the behavioral description file 108 to which the logic simulation processing device inputs data.

After all settings are completed, the loader starts the logic simulation processing device.

Figure 2 shows the source code mask file 107 in Figure 1.
An example of the data format is shown. The PSW 201 indicates a logical simulation start address, a system control mask, and the like. 1N5T 202 indicates an instruction address for locating an instruction and an instruction mnemonic operand, respectively.

LA indicates a load address instruction, L indicates a load instruction, ST indicates a store instruction, and BCT indicates a branch instruction, and these are the test instruction string of the logic verification program.

FNC203 is a behavioral description. That is, the DS statement declares signals named DM, Y, and sets the initial value to zero. The next ON statement means that when C8AD becomes L, the following < EX statement will be executed at that timing, and this EX statement uses the TLB (Translation Look Aside Buffer). Pseudo-logic T L B M I S that executes the process to cancel
S is running, and the next EX statement sets the DMY signal value to 1.
Fixed to 1 during 0 cycles. In the following ON statement and EX statement, when both the DATEND and DMY signals become 1,
This describes the operation of setting the 5TBUSY signal to 1 for 5 cycles.

When the logic verification program test command sequence is executed by the logic simulation processing device 2 according to the settings described in F,
The above-mentioned behavioral description causes TLB cancellation, address translation processing, and store operation busy state to occur simultaneously, making it possible to test in a complex environment that cannot be executed using only the test instruction sequence.

〔Effect of the invention〕

As described above, according to the present invention, when creating the logic verification program source that runs on the logic simulator L, it is possible to simultaneously set the logic signals, drive timing, etc. using the behavioral description, so the program source and simulation environment settings can be made. It becomes possible to centrally manage information and efficiently perform highly accurate logic verification.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the logical simulation environment setting method of the present invention, and FIG. 2 is a diagram showing an embodiment of the data format of a source code mask file. In the figure, 103... data input section, 104... compiler, 105... loader, 106... source code analysis section, 107... source code mask file, 1
08...Behavior description file, 110...Logic simulation processing device.

Claims (1)

[Claims] 1. In a logic simulation that simulates the operation of a logic circuit, means for inputting a test instruction string, initial setting conditions, and a behavior description section, means for compiling the test instruction string, and the test instruction A logical simulation environment setting method comprising: means for loading the sequence and the initial setting conditions into a pseudo memory to execute a logical simulation; and means for delivering the behavioral description part to a logical simulation processing device. 2. The logic simulation environment setting method according to claim 1, wherein the test instruction sequence and the behavioral description section are managed as the same source code in a source code master file. 3. Claim 1, wherein the behavior description section sets a logical signal name, its logical value, and drive timing.
The logical simulation environment setting method described.