JP2943590B2 - Interpreted simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation of an electric logic circuit, and more particularly to a simulation method of a logic circuit using a hardware description language.

[0002]

2. Description of the Related Art In recent years, in designing a large-scale logic circuit, a functional design of an entire circuit is firstly started from a bottom-up design method in which a gate-level circuit drawing is written and an overall circuit is formed by combining the drawings. Do
At that stage, we are moving to a top-down design method in which we omit functional leaks and interfaces, divide them into functional blocks, and further divide each block into blocks in the same way. An essential tool for realizing the top-down design is a hardware description language. Using a hardware description language that supports everything from gate-level descriptions to abstract behavioral descriptions,
The top-level functional design is described at an abstract operation level, the entire circuit is verified, and then the entire circuit is divided into blocks, and each block is further described at an operation level. These steps are repeated, and after some simplification, the circuit is reduced to a gate-level circuit by hand or by a logic synthesis tool, and detailed verification such as timing is proceeding. However, some hardware description languages, unlike general programming languages, cannot completely determine the object structure during analysis of the source program. For example, a hardware description language
IEEE Std 1076-1987 and VHDL language
Elab as described in IEE Std 1076-1993
Until oration, its overall structure is not determined. An example
In example, entity A is generic (WIDTH: integer: = 8); port (A: in bit vector (0 to WIDTH-1); B: out bit vector (0 to WIDTH-1)); end A; and so on If the interface of entity A is defined U0: A generic map (WIDTH => 4) port map (A => sig1, B =>sig2); If called with component instantiation, the bit width of A, B will be ing to 4 but, U0: a generic map (wIDTH => 16) port map (a => sig1, B =>sig2);that's, the bit width becomes 16. In a more complex example, entity B is generic ( W: integer; ); port ( C: in bit_vector (0 to W-1) D: out bit_vector (0 to w-1) ): end B: architecture arc of B is component A genric ( WIDTH: integer: = 8 ); port ( A: in bit_vector (0 to WIDTH -1); B; out bit_vector (0 to WIDTH-1) ); end component; begin U0: A generic map (WIDTH => W) port map (a => C, B =>D); end arc; as described are possible. In this way, there are many layers
The interface can be determined until elaboration
It is possible to write such a description. At first glance normal compa
This is similar to a link in an
For file-based languages, the interface is
It is not changed by the statement. Therefore, VHD
Conventional method for programming languages such as L language
This approach increases development efficiency and maintainability.
It will be damaged. The present invention solves the above matters.
Things. In order to simulate with a source program written in such a language, at the time of language analysis,
Generate a final object by simply creating a source program in any programming language that can be created independently of execution and using it to create the entire structure, and then executing the source program And a procedure for performing a simulation is required.

Conventional Japanese Patent Application Laid-Open No. 62-290939 deals with the replacement of a dynamic execution instruction corresponding to a program modification. Was not taken into account.

[0004]

The above-mentioned prior art has a structure in which the execution object automatically generates itself, so that the process in which the final object is actually constructed is directly performed. Uncontrollable, it takes a lot of man-hours to develop the simulator, it needs to be recompiled to incorporate information for the debugger, and it takes a long time until the simulation is re-executed even if a small hardware description language is changed. There was a disadvantage of becoming.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for converting a hardware description language whose object structure cannot be determined by language analysis into intermediate code, and executing the object by an intermediate language interpreter.

Therefore, a hardware description language in which the object structure of a source program cannot be completely determined at the time of language analysis by a compiler, and the entire object structure is determined only when a part of the language analysis result is executed. In the logic simulation of
A header including information on an intermediate code block generated in executable statement units independent of the object structure of the source program, a signal object linking the intermediate code block, and a block name and a function name of each instance called from the intermediate code block; Generating intermediate code including information, interpreting the header information and the intermediate code block by an intermediate language interpreter, determining a final object structure, and expanding and executing the final object in a memory. And a step.

[0007]

Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1 showing the processing steps of one embodiment of the present invention, a hardware description language 1 for storing a source program described in a hardware description language and a source program of the hardware description language 1 are used as an intermediate. It includes a compiling step 2 for converting the intermediate code 3 into a code 3 by a compiler, and an intermediate language interpreter step 4 for interpreting the intermediate code 3 by an intermediate language interpreter and expanding it in a memory.

Next, each stage of the processing of this embodiment will be described.

[0010] Referring to FIG. 2, in which a source program is converted into intermediate code by a compiler and expansion into memory is performed by an intermediate language interpreter, the uppermost block 5 of the intermediate code converts the sub-block 6 into an instance 8 named COMP. An element 1 to 3 of an array signal 7 named S declared in the top-level block 5 and ranging from 0 to 4 is connected to an array port 9 named A of the sub-block 6 and ranging from 0 to 2. This shows the result of converting the hardware description language 1 having the following content into the intermediate code 3 by the compiler 2 and finally expanding it in the memory by the intermediate language interpreter 4 to determine the object structure.

First, when the hardware description language 1 is compiled by a compiler (step 2), when the uppermost block 5 is compiled, a signal 7 whose name is S and whose range is 0 to 4 is the header information at the time of compiling the uppermost block 5. Information indicating that the signal can be used in 5 is written. In the executable statement, a code for calling the instance 8 named COMP and information indicating that signals 1 to 3 of the signal S7 are connected to the port of the instance are written. When the sub-block 6 is compiled, information that an array port 11 having a name A and a range of 0 to 2 can be used in the sub-block 6 is written as header information, and an executable statement is written. At this time,
The link between the block 5 and the lower sub-block 6 is not performed.

Next, the intermediate code 3 as a compilation result
Is read and executed by the intermediate language interpreter (step 4). When the header information of the top block is read, the signal is declared.
And the head address of the secured area is substituted for the signal 4 pointer. When the analysis of the header information part is completed, the process proceeds to the analysis of the executable statement. Since there is an instance in the executable statement, if the name of COMP is made to correspond to the address of the subblock 6 generated, the analysis of the top block is temporarily interrupted and the analysis of the subblock 6 is started. It can be seen from the header information of the sub-block 6 that there is an array port 11 having a name A and a range of 0 to 2. Since signals 1 to 3 of the uppermost block 5 are assigned to the array port 11, the address of the area 1 of the area 10 secured earlier is assigned to the port 11 pointer. When the analysis of the sub-block 6 is completed, the analysis of the uppermost block 5 is restarted.

When the entire structure is determined as described above and the object is completely expanded in the memory, the simulation can be started. Gener in header of top-level block 5
There is an ic value of WIDTH: = 8 and the declaration 7 of signal S is S (
(0 TO WIDTH-1), it becomes S (0 TO 7) and
Eight areas are secured in the file. Thus, the solution of the header part
Analysis and part of the executable statement are executed alternately to determine the entire structure.
You.

[0014]

By generating an intermediate code in block units, it is possible to generate an intermediate code that does not depend on the structure, and it is possible to minimize re-analysis processing when the description language is changed. By duplicating blocks for each instance and creating the entire structure, it is possible to reduce the simulator development man-hour without the need for complicated stack management, and to debug because the debugger information enters the intermediate code. This has the effect that there is no need to recompile between time and normal execution.

[Brief description of the drawings]

FIG. 1 is a diagram showing processing steps of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a process of interpreting an intermediate code according to the present invention.

[Explanation of symbols]

1 Hardware description language source program 2 Compiler that converts hardware description language source program into intermediate code 3 Intermediate code that divides source program into header information and executable statements in block units 4 Analyzes intermediate code to determine entire structure Intermediate language interpreter for executing simulations by expanding objects in memory.

Claims (1)

(57) [Claims] An object structure of a source program cannot be completely determined during language analysis by a compiler.
In a logic simulation of a hardware description language in which the entire object structure is determined only when a part of the language analysis result is executed, an intermediate code generated for each execution statement independent of the object structure of the source program Generating an intermediate code including a signal object linking a block and the intermediate code block, and header information including information of a block name and a function name of each instance called from the intermediate code block; and Determining a final object structure by interpreting the block by an intermediate language interpreter, expanding the final object in a memory, and executing a logic simulation , comprising the steps of: