JPH01266676A - Logical simulation processor - Google Patents

Abstract

PURPOSE:To execute a logical simulation including a logical operation at an operation describing language part at a high speed by providing a means to convert logic describing data into logical data suitable for the simulation and a simulation processing means. CONSTITUTION:The logic describing data stored in a logic describing file 2 are converted into the logical data expressed as a table and suitable for the simulation by a logic compiling part 6 and stored in a simulation master file 3. A simulation processing part 7 executes the logical simulation using the logical data expressed as the table and stored in the file 3. Further, the processing part 7 executes the logical simulation repeatedly by changing input data to be given to a simulation object logical circuit using the table-formed logical data stored in the file 3 as long as the logic describing data are not changed. Thus, the logical simulation including the logical operation at the operation describing language part can be executed at a high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic simulation processing device for digital logic circuits, and in particular to a logic simulation device suitable for quickly verifying the logic operations of large-scale logic circuits. It is related to.

[Conventional technology]

When designing large-scale computers, VLSIs (large-scale integrated circuits), and the like, the logic scale of the logic circuits to be designed is large, so high-speed logic simulation is required. For this reason, recently, logic simulation processing devices equipped with dedicated hardware for logic simulation have been developed.

For example, regarding a logic simulation processing device equipped with dedicated hardware and designed to perform processing at high speed, there is a logic simulation processing device as described in, for example, Japanese Patent Application Laid-open No. 137663/1983.

By the way, in logic simulations performed when designing large-scale computers, it is recommended to use a logic simulator that can handle hardware models based on behavioral descriptions written in a register transfer level logic description language and logic gate connection descriptions written in a gate level logic description language. Perform logical simulations using For example, Information Processing Society Papers, v
ol, 21. No.

5. Sep., 1980. pp354=365.
"Logical Simulation of Ultra-Large Computer HI TACM-200H" describes an example of logic simulation performed when designing such a large-sized computer.

[Problem to be solved by the invention]

However, in the logic simulation processing device that performs high-speed processing as described above, logic gates that perform logic simulation of a hardware model using logic gates and gate connection descriptions written in a gate connection description language such as a gate level logic description language. For processing, dedicated hardware is installed to enable high-speed processing, but the logic processing of the behavioral part described in a behavioral description language such as a register transfer level logic description language is particularly difficult to achieve at high speed. It is not configured to be able to process it.

For this reason, if the number of logical operation parts included in the behavioral description language part increases, sufficient performance cannot be expected in the logic simulation operation including the logical operation of the behavioral description language part, and even though dedicated hardware is provided, However, there is a problem in that the logic simulation processing may not be sufficiently accelerated.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic simulation processing device that can perform logic simulations including logic operations of a behavioral description language portion at high speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention performs logic simulation processing of a logic gate model using a gate connection description language that describes the connection relationship of logic gates, and a behavioral description language that describes the logical behavior of changes in signal states. In a logic stain/negration processing device that performs logic simulation processing according to The present invention is characterized in that it has a processing means that performs logic simulation processing in integration with the gate.

[Effect]

According to the above means, the logic simulation processing device is provided with a conversion means for converting a logical operation part of a behavioral description language into a gate connection description language as a virtual gate.

This conversion means converts the logical operation part of the behavioral description language into a virtual gate of the gate connection description language, integrates the virtual gate with other logic gates of the gate connection description language, and performs logic simulation processing.

In this way, the logical operation part written in the behavioral description language can be integrated into the logic gate of the gate connection description language and processed in a unified manner.1 For example, the processing of the gate connection description language part can be processed using dedicated hardware. This makes it possible to perform high-speed processing even in logic simulations involving logical operations by the Behavioral Description Language Committee.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 shows a logic simulation according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of a motion processing device. 1st
In @, 1 is a logic simulation processing device, 2 is a logic description file, 3 is a simulation master file, 4 is a simulation data file, and 5 is a simulation result file. Further, numeral 6 is a logic compiling section, and numeral 5 is a simulation processing section. The logic simulation processing unit 1 performs logic simulation by referring to the data of each file using the logic compiling unit 6 and simulation processing unit 7, which are main components. Logic description data specifying a logic circuit to be subjected to logic simulation is stored in a logic description file 2.

□Logic description file 2 includes gate-level logic description written in gate connection description language (gate-level logic description language) that describes the connection relationships of logic gates, and behavioral description language (describes logical operations based on data and signal changes).
Register transfer level logic description data written in register transfer level logic description language (register transfer level logic description language) is stored. These logic description data are processed by the logic compiler 6
The data is converted into table-expressed logical data suitable for simulation and stored in the simulation master file 3. Then, using the table-expressed logical data stored in the simulation master file 3, the simulation processing unit performs a logical simulation. In addition, unless the logic description data is changed, the simulation processing unit uses the logic data in the form of a table stored in the simulation master file 3, and changes the input data given to the logic circuit to be simulated. Perform logical simulations at times.

The input data given to the logic circuit to be simulated here is supplied from the simulation data file 4.

The simulation data file 4 stores microprograms, test programs, external input signal values necessary to operate the logic circuit to be simulated, and commands for specifying how to edit simulation results. .

After the simulation results are stored in the simulation result file 5, they are edited and output as a list from a printer device (not shown), and are also output to a video display terminal device (not shown) according to the designer's instructions. Is displayed.

Next, the operation of such a logic simulation processing device will be specifically explained.

FIG. 2a is a diagram showing an example of a logic circuit to be simulated. The logic circuit in this example is a logic circuit 20 that is a combination of five AND gates u, V, W, X, and y. The logic circuit 20 is described using a gate-level logic description language, and the circuit configuration is specified by logic description data. As mentioned above, the logic description data describing the logic circuit 20 is converted by the logic compiler 6 into logic data in a table representation suitable for simulation, and converted into a format that can be processed on the logic simulation processing device to perform the logic simulation. will be held.

FIG. 2b is a diagram showing an example of a logic circuit table of logic data in which the logic description data of the logic circuit 20 of FIG. 2a is expressed as a table. As shown in FIG. 2b, the logic circuit table 21 includes gate name 22.function/signal value 23.
1st person blade tip address 24. 2nd person blade tip address 25. A column is provided to hold each data of the cutting edge address 26. The gate name column 22 holds data on names that identify each logic gate. In the column of function/signal value 23, 1. Along with functions such as AND, OR, FOR, etc. for each logic gate.

The signal value (1, O, etc.) of the logic gate is held.

1st person's cutting edge address 24 and 2nd person's cutting edge address 25
The column holds address data indicating the connection destination of the input terminal of the logic gate. Also, the cutting edge address 26
The column holds address data indicating the connection destination of the output terminal of the logic gate.

For example, the logic gate U is an AND gate, and the AN
It is shown that signals from terminal a and terminal S are input to the input terminal of the D gate, and a logic output signal is output from the output terminal of the AND gate to gate X and gate y. Also, the first cutting edge address 24 of logic gate °X
In the column, a bar added above gate U indicates that the negation of the signal value input from gate U is input, and similarly, the signal value input from gate V is also input. , indicates that the negation of that signal value is input. The logic description data is expressed as a table in the logic circuit table 21, and the simulation processing unit 7
performs logic simulation processing at high speed.

FIG. 3 is a diagram showing an example of a command sequence in which the logical operation of a logic circuit is described in a behavioral description language. Command string 30
The logic description given by . . . describes the logic operations of the logic gate X and the logic gate y of the logic circuit 20 of FIG. 2a. In the simulation process of logical behavior using commands in this behavior description language, if the conditions described in the ON command are satisfied, the process described in the EX command is executed (after a specified time has elapsed), and the logic of the logical behavior is executed. A simulation is run. Therefore, by executing the command sequence 30 as described herein, the logical operations of the logic gates X and y of the logic circuit 20 are executed. The conditional expression rA=Q&B=OJ of the ON command 31 indicates that the condition is satisfied when the signal A has the signal value "Ojj" and the signal B has the signal value "O"'. If it holds true,
In the processing of the next EX command 32, the signal value is set to “1”.
Processing is performed. Therefore, by processing the combination of the ON command 31 and the EX command 32, a logical operation equivalent to the logical operation of the logic gate X (FIG. 2a) in the logic circuit 20 can be performed. That is, the logic gate
When the output signal B becomes the signal value "0", the logic value of the logic output signal is set to "1".

On the other hand, in the ON command 31, the conditional expression rA=o&B=
0" is established, and the condition of ON command 31 is satisfied,
In the processing of the next EX command 32, the output signal is changed to the signal value "
1", so ON command 31 and E
The processing of the combination of the X commands 32 corresponds to the processing of the logic gate x which performs the logic processing of the negative two-manual AND gate. Similarly, ON command 33 and EX command 34
The processing of the combination is equivalent to the logic operation of the logic gate y of the logic circuit 20.

Such a logic gate (logic circuit table: Figure 2b)
logical simulation processing and behavioral description language (
The logic simulation process shown in FIG. 3) is performed by the simulation processing section 7 as shown in FIG.

FIG. 4 is a flowchart showing logical simulation processing performed by the simulation processing section F. This logic simulation process will be explained with reference to FIG.

First, in step 41, an input value application process is performed in which an input value is given to a logic gate, and then step 4
At 2, logic gate processing is performed. Logic gate processing is performed at high speed by dedicated hardware that processes data in the logic circuit table. Next step 4
In step 3, it is determined whether or not there is still logic gate processing, and while the logic gate processing remains, the process returns to step 42 to continue the logic gate processing. When the logic gate processing is completed, the result is received as the primary step and the behavioral description language processing of step 44 is performed. In the next step 45, it is similarly determined whether there is any unprocessed behavioral description language processing, and while the behavioral description language processing remains, the process returns to step 44 to continue the behavioral description language processing. When the behavioral description language processing is completed, the next determination processing of step 46 is performed. In the determination process of step 46, it is determined whether or not there is a logic gate process that has occurred based on the result of the behavioral description language process.If there is a logic gate process that has occurred, the process returns to step 42 again and from step 42 Continue processing. In the determination process of step 46, if there is no logic gate process that has occurred, all processes have been completed, so the timer update process is performed in the first step 47, and the timer time updated in the next step 48 is the end time. Determine whether or not. In step 48, if it is not the end time, the process from step 41 is repeated, and when the end time is reached, the process is terminated.

In this way, logic simulation processing using logic gate processing and behavioral description language processing is executed assuming various cases by changing input data, input conditions, etc.

By the way, during the logic simulation process, a part where the logic needs to be changed occurs, and the logic designer, for example,
Make logic changes to logic circuit 2G (Figure 2a),
When the logic is changed to the logic circuit 50 having the configuration shown in FIG. 5a and a logic simulation process is performed, the process is performed as follows.

The logic change is made by changing the output signal E of the AND gate y, which receives the output signal A of the AND gate U and the output signal C of the AND gate W, as shown in FIG. 5a, as shown by the broken line. , the logic is changed so that the negative value of the output signal B of the AND gate v and the output signal C of the AND gate W becomes the output signal from the OR gate 2 to which it is input. When making such a logic change, originally the gate connection description data in the gate level logic description language of the logic description file that is the logic master is changed, but changing the logic master file data takes time and effort to update. In addition, preprocessing for logical simulation also takes time.

For this reason, data changes and preprocessing for logic changes are minimized, and changes are made only to test data written in a behavioral description language for logic simulation, so that the logic changes are equivalent to logic changes using logic gates. Make it.

Here, the logic change process is performed by describing the logic gate whose logic is to be changed by writing a command string (see FIG. 3) in the register transfer level behavioral description language as described above. In this case, as shown in FIG. 5b, a string of commands 52 and 53 of the behavioral description language corresponding to the logic gate part whose logic is to be changed is added to the command string 51 of the behavioral description language in which the test data is set. Add. The logic gate portion based on the command string of this behavioral description language is transformed into a virtual logic gate by a conversion process to be described later, into a format that can be processed in the same manner as other logic gates in the logic circuit table. As a result, the virtual logic gate set by the command 82.53 shown in FIG. 5b becomes the OR logic virtual logic gate 2 shown by the broken line in the logic circuit 50 of FIG. 5a. The connections and virtual logic gates 2 indicated by broken lines do not actually exist, but are represented virtually. By providing the virtual logic gate 2, the output signal E to the terminal 1 is not the output signal from the AND gate y, but
It will be temporarily replaced by the output signal of the virtual αR logic gate 2.

FIG. 6 is a diagram showing an example of a logic circuit table of logic data in which the logic description data of the logic circuit 50 of FIG. 5a is expressed as a table. Logic circuit table 6 shown in Figure 6
0 is basically the same as the logic circuit table 21 (Fig. 2b), but a column for holding data of virtual output destination/condition 61 is added, and a correspondence for adding a virtual logic gate is added. has been made. That is, the logic circuit table 60 has the same gate names 22, functions/signal values 23 . 1st person blade tip address 2
4. 2nd person blade tip address 25. The table has a format in which a column for holding data for the virtual output destination/condition 61 is added to a column for holding each data for the cutting edge address 26. Further, a virtual logic circuit table 62 similar to the logic circuit table 21 is provided in order to represent the virtual logic gate itself in a table. Virtual logic circuit table 62
The same gate names 222 functions and signal values 23 as in the logic circuit table 21 are shown in the table. 1st person blade tip address 24. 2nd person blade tip address 25. A column is provided to hold each data of the cutting edge address 26. Each virtual logic gate expressed on the virtual logic circuit table 62
It is pointed to by the address data held in the virtual output destination/condition column 61, and is connected from other logic gates.

In this way, for a virtual logic gate for performing a logic change expressed by a conditional expression in a behavioral description language, the table representation of the virtual logic circuit table 62 is used to change the table representation of other logic gates in the logic circuit table 60. Since the data format is the same as that of , the simulation processing unit 7 can process virtual gates added by logic changes in an integrated manner without particularly distinguishing them, and can perform logic simulation processing at high speed. Furthermore, the characteristic feature of the logic circuit table 60 corresponding to such a virtual logic gate is that the table representation of the original logic circuit table 21 is left unchanged without being changed. Therefore, it is easy to remove the virtual logic gate and restore it. That is, the logic circuit table 60 is a table representation of the logic circuit table 21 with a column for virtual output destination/condition 61 added, and the logic circuit table 21
The table representation of remains unchanged. Therefore, when performing the process of returning the logic circuit table 60 to the original logic circuit table 21, the process of returning the logic circuit table 60 to the original logic circuit table 21 can be easily performed by simply removing the added column of virtual output destination/condition 61.

Next, data held in the column of virtual output destination/condition 61, which indicates the connection between a real logic gate expressed in a table and a virtual logic gate expressed in a table expressed in a behavioral description language, will be explained. As can be easily seen from FIG. 5a, AND gate U and AND gate x are independent of virtual logic gate 2. Therefore, the data in the virtual output destination/condition 61 column for gates U and X is 'floating'. This indicates that there is no connection relationship at all.

Then, AND gate V and AND gate W are virtual OR
An output terminal is also connected to the gate z.

Therefore, the data in the virtual output destination/condition 61 column for gates V and W is "virtual gate z#2." E is output to the terminal, but since priority is given to the processing described by the EX command 53 of the behavioral description language, the data in the column of virtual output destination/condition 61 for gate y is ``inhibited''. This indicates that output to the terminal indicated in the field of edge address 26 of gate y is suppressed. As a result, in the virtual logic circuit table 62 formed in response to the processing of the ON command 52 and the EX command 53, the negative output to the terminal indicated in the column ``cutting end address 26'' of the virtual logic gate 2 is changed as a result. The output is to the terminal as . By using the "inhibition" condition of the data in the virtual output destination/condition 61 column, for example, it is possible to limit the output light of the output signal of the AND gate v to the virtual logic gate 2 only. In that case,
The data in the virtual output destination/condition 61 column for gate y is 'virtual gate 2. After completing the logic change using only test data using a behavioral description language,
If you want to return to the original logic circuit table, change the virtual output destination/
By setting all the data in the column of condition 61 to "floating", it can be easily restored to its original state.

Next, a process for creating a virtual logic circuit table for a virtual gate for logic modification using a behavioral description language will be described. The process of creating such a virtual gate is performed by, for example, the logic compiler 6.

FIGS. 7a and 7b are flowcharts showing the process of creating a virtual logic circuit table for a virtual gate from a behavioral description language command.

Here, the process of creating a virtual logic circuit table from the command strings 52 and 53 shown in FIG. 5b will be explained as an example. Referring to FIG. 7a, first, in step 71, ON command syntax analysis processing is performed to divide the ON command conditional expression into a signal condition and a determination condition. Next step 7
In the second input signal connection process, the input optical address is determined from the signal conditions.

In this input signal connection process, the gate address from which the corresponding signal is output is determined from the table representation of the logic gate and is used as the input optical address. Note that if the signal condition is 110", it is a negative input. Next, the virtual gate creation process of step 73 is performed. In this virtual gate creation process, the function of the virtual gate is determined based on the 1 judgment condition, and the virtual gate is input along with the input optical address. Register in the logic circuit table.Next step 7
In step 4, EX command syntax analysis processing is performed to create signal conditions from the EX command. Next, as shown in FIG. 7b, output signal connection processing is performed in step 75. In the output signal connection process, the gate address to which the corresponding signal is output is determined from the table representation of the logic gate and is used as the cutting edge address. Note that when the signal condition is O'', a negative output is made.Next, the logic gate output suppression process of step 76 is performed.In this process, the virtual output destination of the table representation of the logic gate to which the output signal corresponds is determined. Set the data in the condition column to "suppression" to suppress the output from the logic gate side that competes with the output light of the output terminal.Also, the data in the virtual output destination/condition column of the table representation of other logic gates is also supported. Through such processing, table representations of the logic circuit table 60 and the virtual logic circuit table 62 corresponding to the virtual logic gates can be created.

As explained above, according to this embodiment, even when the logic is changed to the logic gate of the logic circuit table using only test data using a behavioral description language, the logic can be converted to the same table representation. , can be processed at high speed with a logic simulation processing device, and
It is possible to easily return to the table representation of the logic circuit table before the logic change.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, in a logic simulation processing device, a logical operation part of a behavioral description language is converted into a virtual gate of a gate connection description language, and the virtual gate is converted into another logic gate of a gate connection description language. For example, the gate connection description language part can be processed using dedicated hardware, and the logic simulation process including the logical behavior of the behavioral description language part can be integrated with Also, high-speed processing is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a logic simulation processing device according to an embodiment of the present invention, and FIG. 2a is a
FIG. 3 is a diagram showing an example of a simulation target logic circuit. Figure 2b shows an example of a logic circuit table of logic data in which logical description data of a logic circuit is expressed as a table. Figure 3 shows an example of a command string that describes the logical operation of a logic circuit in a behavioral description language. FIG. 4 is a flowchart showing the logic simulation process performed by the simulation processing unit F, FIGS. 5a and 5b are diagrams explaining the logic change process in the logic simulation, and FIG. FIGS. 7a and 7b are diagrams showing an example of a logic circuit table of logic data in which logic description data is expressed as a table. FIG. In the diagram! ...Logic simulation processing device, 2...
- Logic description file, 3... Simulation master file, 4... Simulation data file, 5... Simulation result file, 6... Logic compiling section, F... Simulation processing section.

Claims (1)

[Claims] 1. In a logic simulation processing device that performs logic simulation processing of a logic gate model using a gate connection description language that describes connection relationships of logic gates, and also performs logic simulation processing using a behavioral description language that describes logical behavior of changes in signal states. , comprising a conversion means for converting a logical operation part of a behavioral description language into a virtual gate of a gate connection description language, and a processing means for integrating the virtual gate with other logic gates of the gate connection description language and performing logic simulation processing. A logical simulation processing device characterized by: