JPH03240251A - Method of repairing defective semiconductor chip - Google Patents
Method of repairing defective semiconductor chipInfo
- Publication number
- JPH03240251A JPH03240251A JP9037569A JP3756990A JPH03240251A JP H03240251 A JPH03240251 A JP H03240251A JP 9037569 A JP9037569 A JP 9037569A JP 3756990 A JP3756990 A JP 3756990A JP H03240251 A JPH03240251 A JP H03240251A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- defective semiconductor
- wire
- pattern
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 230000002950 deficient Effects 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title abstract description 23
- 239000000853 adhesive Substances 0.000 claims abstract description 15
- 230000001070 adhesive effect Effects 0.000 claims description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000006023 eutectic alloy Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000843 powder Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Supply And Installment Of Electrical Components (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
混成集積回路等の半導体装置に実装された不良半導体チ
ップのりペア方法に関し、
低コストの不良半導体チップのりペア方法を提供するこ
とを目的とし、
回路基板にワイヤボンデング実装された不良半導体チッ
プのリペアに際し、該不良半導体チップの電極と該回路
基板のパターンとを接続している、アースワイヤ以外の
全信号ワイヤを取り外し、次に、該不良半導体チップの
上面に導電性接着剤を塗布して、該不良半導体チップ上
に良品半導体チップをグイボンデング・重量し、その後
、該良品半導体チップの電極と該回路基板の信号パター
ンを他の信号ワイヤで、該良品半導体チップのアース電
極と該回路基板のアースパターンとを他のアースワイヤ
で、それぞれワイヤボンデング接続する構成とする。[Detailed Description of the Invention] [Summary] The present invention relates to a method for pairing a defective semiconductor chip mounted on a semiconductor device such as a hybrid integrated circuit, and aims to provide a method for pairing a defective semiconductor chip at a low cost. When repairing a defective semiconductor chip that has been bonded, all signal wires other than the ground wire connecting the electrodes of the defective semiconductor chip and the circuit board pattern are removed, and then the top surface of the defective semiconductor chip is removed. A conductive adhesive is applied to the defective semiconductor chip, and a good semiconductor chip is bonded and weighed on top of the defective semiconductor chip.Then, the electrodes of the good semiconductor chip and the signal pattern of the circuit board are connected using other signal wires, and then the good semiconductor chip is bonded to the defective semiconductor chip. The ground electrode of the chip and the ground pattern of the circuit board are connected by wire bonding using other ground wires.
本発明は、混成集積回路等の半導体装置に実装された不
良半導体チップのりペア方法に関する。The present invention relates to a method for pairing defective semiconductor chips mounted on a semiconductor device such as a hybrid integrated circuit.
［従来の技術〕 第３図は混成集積回路等の半導体装置の斜視図である。[Conventional technology] FIG. 3 is a perspective view of a semiconductor device such as a hybrid integrated circuit.
図において、１はセラミック基板、ガラス繊維入エポキ
シ樹脂基板等の回路基板である。In the figure, 1 is a circuit board such as a ceramic board or an epoxy resin board containing glass fiber.
回路基板１の実装面に、所望数の半導体チップ１０、及
び抵抗体、コンデンサ等の受動部品８を実装することで
、半導体装置が構成されている。A semiconductor device is constructed by mounting a desired number of semiconductor chips 10 and passive components 8 such as resistors and capacitors on the mounting surface of the circuit board 1.
半導体チップ１０は、グイボンデング用パターン（図示
省略）上に、導電性接着剤（例えばＡｇ等の微粉末を含
む導電性エポキシ樹脂）５を使用してフェー゛スアップ
にダイボンデングされている。The semiconductor chip 10 is die-bonded face-up onto a die-bonding pattern (not shown) using a conductive adhesive (for example, a conductive epoxy resin containing fine powder such as Ag) 5.
そして、半導体チップ１０の表面に配列した電極と、回
路基板１に配列した信号パターン（図示省略）とは、例
えば金線等の信号ワイヤ１３を用いてワイヤボンデング
接続されている。The electrodes arranged on the surface of the semiconductor chip 10 and the signal patterns (not shown) arranged on the circuit board 1 are connected by wire bonding using signal wires 13 such as gold wires, for example.
また、半導体チップ１０の表面に配列したアース電極と
回路基板１に配列したアースパターン（図示省略）とは
、例えば金線等のアースワイヤ１４を使用してワイヤボ
ンデング接続されている。Further, the ground electrodes arranged on the surface of the semiconductor chip 10 and the ground patterns (not shown) arranged on the circuit board 1 are connected by wire bonding using a ground wire 14 such as a gold wire, for example.
一方、受動部品８は電極と回路基板に配設したパッドと
を半田付けすることで、回路基板１に実装されている。On the other hand, the passive component 8 is mounted on the circuit board 1 by soldering electrodes and pads provided on the circuit board.
なお、グイボンデング用パターンはアースパターンに繋
がっているのが一般である。Note that the gui bonding pattern is generally connected to the earth pattern.
また、導電性接着剤を用いることなく、他のグイボンデ
ング法９例えばＡｕ−３ｉ共晶合金法或いは半田接着法
等により、半導体チップ１０を回路基板１にダイボンデ
ングしているものもある。In addition, there is also a method in which the semiconductor chip 10 is die-bonded to the circuit board 1 by other bonding methods 9 such as the Au-3i eutectic alloy method or the solder bonding method without using a conductive adhesive.
上述のような半導体装置において、半導体チップの不良
が発見された場合には、その不良半導体チップ１０＾を
取替える必要がある。In the semiconductor device as described above, when a defective semiconductor chip is discovered, it is necessary to replace the defective semiconductor chip 10^.
したがって、不良半導体チップ１０＾を回路基板１から
取り外すのであるが、信号ワイヤ１３．アースワイヤ１
４の取り外しは、ピンセット等を用いてワイヤの圧着部
近傍を挟み引っ張ると、圧着部の根元部分でワイヤが切
断する。Therefore, the defective semiconductor chip 10^ is removed from the circuit board 1, but the signal wires 13. Earth wire 1
4 can be removed by pinching and pulling the wire near the crimped part using tweezers or the like, and the wire will be cut at the base of the crimped part.
このように信号ワイヤ、アースワイヤ等の除去作業は容
易である。In this way, it is easy to remove signal wires, ground wires, etc.
一方、導電性樹脂接着法、Ａｕ−３ｉ共晶合金法、半田
接着法等でダイボンデングされた不良半導体チップの除
去は、非常に困難であり、また、除去し得た時にはグイ
ボンデング用パターンが剥離することが多（て、その跡
に他の良品の半導体チップをダイボンデングすることが
出来ない。On the other hand, it is extremely difficult to remove defective semiconductor chips that have been die-bonded using conductive resin bonding, Au-3i eutectic alloy, solder bonding, etc., and when they are removed, the die-bonding pattern peels off. In many cases, it is not possible to die bond other good semiconductor chips in the wake.
したがって、従来は１個でも不良半導体チップが発見さ
れた半導体装置は、他の良品の半導体チップを実装した
状態でその半導体装置を棄却し、新しい半導体装置に取
り替えていた。Therefore, conventionally, if a semiconductor device was found to have even one defective semiconductor chip, the semiconductor device was discarded with other good semiconductor chips mounted thereon and replaced with a new semiconductor device.
したがって、上記従来例のりペア方法では、良品の半導
体チップが棄却されることになり、非常にコスト高であ
るという問題点があった。Therefore, the above-mentioned conventional glue pair method has the problem that good semiconductor chips are rejected and the cost is extremely high.
本発明はこのような点に鑑みて創作されたもので、低コ
ストの不良半導体チップのりペア方法を提供することを
目的としている。The present invention was created in view of these points, and an object of the present invention is to provide a low-cost method for bonding defective semiconductor chips.
上記の目的を達成するために本発明は、第１図に図示し
たように、回路基板１にワイヤボンデング実装された不
良半導体チップ１０Ａのりペアに際し、先ず、不良半導
体チップ１０Ａの電極と回路基板１のパターンとを接続
している、アースワイヤ１４以外の全信号ワイヤ１３を
取り外す。In order to achieve the above object, the present invention, as shown in FIG. Remove all signal wires 13 other than the ground wire 14, which are connected to pattern No. 1.
次に、不良半導体チップ１０Ａの上面に導電性接着剤５
を塗布して、その上に良品半導体チップ１００を載置す
る。そして、加熱して（キュアー温度は約１００℃）導
電性接着剤５を硬化させることで、不良半導体チップ１
０Ａ上に良品半導体チップ１００をダイボンデングし重
量する。Next, conductive adhesive 5 is applied to the upper surface of the defective semiconductor chip 10A.
A good semiconductor chip 100 is placed thereon. Then, by heating (curing temperature is about 100°C) to cure the conductive adhesive 5, the defective semiconductor chip 1 is cured.
A non-defective semiconductor chip 100 is die-bonded onto 0A and weighed.
その後、良品半導体チップ１００の電極と回路基板１の
信号パターン３を他の信号ワイヤ１３０を用いてワイヤ
ボンデングし、さらに良品半導体チップ１００のアース
電極と回路基板１のアースパターン４とを他のアースワ
イヤ１４０を用いてワイヤボソデングするものとする。Thereafter, the electrode of the non-defective semiconductor chip 100 and the signal pattern 3 of the circuit board 1 are wire-bonded using another signal wire 130, and the ground electrode of the non-defective semiconductor chip 100 and the ground pattern 4 of the circuit board 1 are bonded with another signal wire 130. It is assumed that the ground wire 140 is used for wire bonding.
上述のように、良品半導体チップ１００は、裏面に形威
された導電性接着剤層を介して、不良半導体チップ１０
Ａ上に重量されている。As described above, the good semiconductor chip 100 is attached to the defective semiconductor chip 10 via the conductive adhesive layer formed on the back surface.
It is weighted on A.
一方、この導電性接着剤層は、不良半導体チップ１０Ａ
のアースワイヤ１４を介してアースパターン４に接続さ
れている。On the other hand, this conductive adhesive layer is attached to the defective semiconductor chip 10A.
It is connected to the ground pattern 4 via a ground wire 14 .
良品半導体チップの裏面に形威された導電性接着剤層が
、アース層の機能を兼ねているので、良品半導体チップ
は不良半導体チップ上にグイボンデングされているにも
係わらず、その電気的特性は回路基板のグイボンデング
用パターン上に、直接グイボンデングされたものと殆ど
同じ電気的特性を備えている。The conductive adhesive layer formed on the back side of a good semiconductor chip also functions as a ground layer, so even though a good semiconductor chip is bonded onto a bad semiconductor chip, its electrical characteristics remain the same. It has almost the same electrical characteristics as the one directly bonded onto the pattern for bonding on the circuit board.
また、不良半導体チップを除去することなく、不良半導
体チップの上に良品半導体チップを重量するのであるか
ら、もとの回路基板は勿論のこと、他の半導体チップを
そのまま使用することができ、且つ重量するグイボンデ
ング作業が容易であるので、低コストの不良半導体チッ
プのリペア方法である。In addition, since a good semiconductor chip is placed on top of the defective semiconductor chip without removing the defective semiconductor chip, not only the original circuit board but also other semiconductor chips can be used as is. Since the heavy bonding work is easy, it is a low-cost method for repairing defective semiconductor chips.
（実施例〕
以下図を参照しながら、本発明を具体的に説明する。な
お、全図を通じて同一符号は同一対象物を示す。(Example) The present invention will be specifically described below with reference to the drawings.The same reference numerals indicate the same objects throughout the drawings.
第１図は本発明方法の工程を示す断面図であり、第２図
は本発明方法の実装作業終了後の斜視図である。FIG. 1 is a sectional view showing the steps of the method of the present invention, and FIG. 2 is a perspective view of the method after the mounting work is completed.
第１図（ａ）に示したように、回路基板ｌの実装面の所
望の位置に、グイボンデング用パターン２を設け、さら
にそれぞれのパッド部分がグイボンデング用パターン２
の周辺に配列するように、信号パターン３及びアースパ
ターン４を、回路基！１の実装面に形威しである。As shown in FIG. 1(a), a Gui bonding pattern 2 is provided at a desired position on the mounting surface of the circuit board l, and furthermore, each pad portion is connected to the Gui bonding pattern 2.
The signal pattern 3 and the ground pattern 4 are arranged around the circuit board! This is similar to the implementation aspect of 1.
なお、グイボンデング用パターン２とアースパターン４
とは繋がっている。In addition, pattern 2 for Gui bonding and earth pattern 4
is connected.
半導体チップ１０は、グイボンデング用パターン２上に
、導電性接着剤（例えばＡｇ等の微粉末を含む導電性エ
ポキシ樹脂）５を使用してフェースアップにグイボンデ
ングされ、さらに、半導体チップ１０の表面に配列した
電極と、信号パターン３のパッド部分とを、金線等の信
号ワイヤ１３を用いてワイヤボンデング接続しである。The semiconductor chip 10 is bonded face-up onto the bonding pattern 2 using a conductive adhesive (for example, a conductive epoxy resin containing fine powder such as Ag) 5, and is further arranged on the surface of the semiconductor chip 10. The electrode and the pad portion of the signal pattern 3 are connected by wire bonding using a signal wire 13 such as a gold wire.
また、半導体チップ１００表面に配列したアース電極と
アースパターン４のパッド部分とを、金線等のアースワ
イヤ１４を使用してワイヤボンデング接続しである。Further, the ground electrodes arranged on the surface of the semiconductor chip 100 and the pad portions of the ground pattern 4 are connected by wire bonding using a ground wire 14 such as a gold wire.
なお、第１図の右側に図示した半導体チップは、不良半
導体チップ１０Ａである。Note that the semiconductor chip illustrated on the right side of FIG. 1 is a defective semiconductor chip 10A.
上述のような不良半導体チップ１０Ａのリペアは、先ず
第１図（ｂ）に示したように、不良半導体チップ１０Ａ
の電極と回路基板ｌのパターンとを接続している、アー
スワイヤ１４以外の全信号ワイヤ１３を取り外す。To repair the defective semiconductor chip 10A as described above, first, as shown in FIG. 1(b), the defective semiconductor chip 10A is
Remove all signal wires 13 other than the ground wire 14 connecting the electrodes of 1 and the patterns of circuit board 1.
なお、取り外し作業は、ピンセット等を用いて電極との
圧着部近傍の信号ワイヤ１３部分を挟み引っ張り、圧着
部の根元部分でワイヤを切断し、次に信号パターンのバ
ッドとの圧着部近傍の信号ワイヤ１３部分をビンセット
等で挟み引っ張り、圧着部の根元部分でワイヤを切断す
ることで、信号ワイヤ１３を取り外す。To remove the signal, use tweezers or the like to pinch and pull the signal wire 13 near the crimped part with the electrode, cut the wire at the base of the crimped part, and then remove the signal near the crimped part with the signal pattern pad. The signal wire 13 is removed by pinching and pulling the wire 13 with a bin set or the like, and cutting the wire at the base of the crimped portion.
次に、第１図（Ｃ）に示すように、不良半導体チップ１
０Ａの上面に導電性接着剤５を塗布する。Next, as shown in FIG. 1(C), the defective semiconductor chip 1
Apply conductive adhesive 5 to the upper surface of 0A.
そして、第１図（ｄ）に示すように、良品半導体チップ
１００の裏面を、不良半導体チップ１０Ａに位置合わせ
して、良品半導体チップ１００を不良半導体チップ１０
Ａ上に載せ、導電性接着剤５で仮接着した後に、赤外線
等を照射して導電性接着剤５を加熱し硬化させ、良品半
導体チップ１００を不良半導体チップ１０Ａ上にグイボ
ンデングし重量する。Then, as shown in FIG. 1(d), the back surface of the good semiconductor chip 100 is aligned with the bad semiconductor chip 10A, and the good semiconductor chip 100 is aligned with the bad semiconductor chip 10A.
A and temporarily bonded with a conductive adhesive 5, the conductive adhesive 5 is heated and cured by irradiation with infrared rays, etc., and the non-defective semiconductor chip 100 is firmly bonded onto the defective semiconductor chip 10A and weighed.
次に第１図（ｅ）に示すように、良品半導体チップ１０
０の電極と回路基板１の対応する信号パターン３のパタ
ーン部分とを、金線等の信号ワイヤ１３０を用いてそれ
ぞれワイヤボンデングする。また、良品半導体チップ１
００のアース電極と回路基板１の対応するアースパター
ン４とを金線等のアースワイヤ１４０を用いてワイヤボ
ンデングする。Next, as shown in FIG. 1(e), a non-defective semiconductor chip 10
The electrode No. 0 and the corresponding pattern portion of the signal pattern 3 on the circuit board 1 are wire-bonded using a signal wire 130 such as a gold wire. In addition, good semiconductor chip 1
The ground electrode 00 and the corresponding ground pattern 4 of the circuit board 1 are wire-bonded using a ground wire 140 such as a gold wire.
したがって、第２図に図示したように、不良半導体チッ
プ１０Ａは回路基板１に導電性接着剤５を介して直接グ
イボンデングされ、良品半導体チップ１００は、不良半
導体チップ１０Ａの上に重量して導電性接着剤５によっ
てグイボンデングされている。Therefore, as shown in FIG. 2, the defective semiconductor chip 10A is directly bonded to the circuit board 1 via the conductive adhesive 5, and the good semiconductor chip 100 is placed on the defective semiconductor chip 10A by weight and conductive. It is bonded with adhesive 5.
即ち、良品半導体チップ１００は、裏面に形成された導
電性接着剤５０層を一介して、不良半導体チップ１０Ａ
上に重量され、この導電性接着剤層は、不良半導体チッ
プ１０Ａのアースワイヤ１４を介して回路基板１のアー
スパターン４に接続されており、良品半導体チップ１０
０の表面に配列したそれぞれの信号電極は、信号ワイヤ
１３０を介して対応する信号パターン３に接続されてい
る。That is, the non-defective semiconductor chip 100 is connected to the defective semiconductor chip 10A through 50 layers of conductive adhesive formed on the back surface.
This conductive adhesive layer is connected to the ground pattern 4 of the circuit board 1 via the ground wire 14 of the defective semiconductor chip 10A, and is connected to the ground pattern 4 of the circuit board 1.
Each signal electrode arranged on the surface of 0 is connected to the corresponding signal pattern 3 via a signal wire 130.
また、良品半導体チップ１００の表面のアース電極は、
アースワイヤ１４０を介して対応する信号パターン３に
接続されている。Furthermore, the ground electrode on the surface of the non-defective semiconductor chip 100 is
It is connected to the corresponding signal pattern 3 via a ground wire 140.
上述のように良品半導体チップ１００がグイボンデング
されているので、良品半導体チ・ンプの裏面に形成され
た導電性接着剤層が、アース層の機能を兼ねている。よ
って、良品半導体チップ１００は不良半導体チップ１０
Ａ上に重量されているにも係わらず、その電気的特性は
回路基板のグイボンデング用パターン上に、直接グイボ
ンデングしたものと殆ど同じ電気的特性を備えている。Since the non-defective semiconductor chip 100 is bonded as described above, the conductive adhesive layer formed on the back surface of the non-defective semiconductor chip also functions as a ground layer. Therefore, the good semiconductor chip 100 is the defective semiconductor chip 10.
Although it is weighted on A, its electrical characteristics are almost the same as those formed by direct bonding on the bonding pattern of the circuit board.
なお本発明方法は、Ａｕ−３ｔ共晶合金法、半田接着法
等でグイボンデングされた、不良半導体チップに適用し
得ることは勿論のことである。It goes without saying that the method of the present invention can be applied to defective semiconductor chips that have been bonded using the Au-3t eutectic alloy method, solder bonding method, or the like.
以上説明したように本発明は、不良半導体チップを除去
することなく、その上に良品半導体チップをグイボンデ
ング・重量するという不良半導体チップのりペア方法で
あって、回路基板は勿論のこと、他の良品の半導体チッ
プをそのまま使用することができ、且つ良品半導体チッ
プを重量するグイボンデング作業が容易であり、従来方
法に較べて非常に低コストであるという、実用上で優れ
た効果がある。As explained above, the present invention is a method for bonding and bonding a good semiconductor chip on top of a defective semiconductor chip without removing the defective semiconductor chip. This method has excellent practical effects in that it is possible to use semiconductor chips as they are, it is easy to perform bonding work for weighing good semiconductor chips, and the cost is much lower than that of conventional methods.
第１図は本発明方法の工程を示す断面図、第２図は本発
明方法の実装作業終了後の斜視図、第３図は半導体装置
の斜視図である。
図において、
１は回路基板、
２はグイボンデング用パターン、
３は信号パターン、
４はアースパターン、
５は導電性接着剤、
８は受動部品、
１０は半導体チップ、
１０Ａは半導体チップ、
１００は良品半導体チップ、
１３．１３０は信号ワイヤ、
１４、１４０はアースワイヤをそれぞれ示す。
第 １ 口FIG. 1 is a cross-sectional view showing the steps of the method of the present invention, FIG. 2 is a perspective view of the semiconductor device after the mounting work of the method of the present invention is completed, and FIG. 3 is a perspective view of a semiconductor device. In the figure, 1 is a circuit board, 2 is a bonding pattern, 3 is a signal pattern, 4 is a ground pattern, 5 is a conductive adhesive, 8 is a passive component, 10 is a semiconductor chip, 10A is a semiconductor chip, 100 is a good semiconductor 13 and 130 are signal wires, and 14 and 140 are ground wires, respectively. 1st mouth
Claims (1)
導体チップ（１０Ａ）のリペアに際し、該不良半導体チ
ップ（１０Ａ）の電極と該回路基板（１）のパターンと
を接続している、アースワイヤ（１４）以外の全信号ワ
イヤ（１３）を取り外し、次に、該不良半導体チップ（
１０Ａ）の上面に導電性接着剤（５）を塗布して、該不
良半導体チップ（１０Ａ）上に良品半導体チップ（１０
０）をダイボンデング・重量し、 その後、該良品半導体チップ（１００）の電極と該回路
基板（１）の信号パターン（３）を他の信号ワイヤ（１
３０）で、該良品半導体チップ（１００）のアース電極
と該回路基板（１）のアースパターン（４）とを他のア
ースワイヤ（１４０）で、それぞれワイヤボンデング接
続することを特徴とする不良半導体チップのリペア方法
。[Claims] When repairing a defective semiconductor chip (10A) mounted on a circuit board (1) by wire bonding, an electrode of the defective semiconductor chip (10A) and a pattern of the circuit board (1) are connected. Remove all signal wires (13) other than the ground wire (14) that are connected to the defective semiconductor chip (
A conductive adhesive (5) is applied to the upper surface of the defective semiconductor chip (10A), and a good semiconductor chip (10A) is placed on top of the defective semiconductor chip (10A).
0) is die-bonded and weighed, and then the electrodes of the non-defective semiconductor chip (100) and the signal pattern (3) of the circuit board (1) are connected to other signal wires (100).
30), the ground electrode of the non-defective semiconductor chip (100) and the ground pattern (4) of the circuit board (1) are connected by wire bonding with another ground wire (140), respectively. How to repair semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9037569A JPH03240251A (en) | 1990-02-19 | 1990-02-19 | Method of repairing defective semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9037569A JPH03240251A (en) | 1990-02-19 | 1990-02-19 | Method of repairing defective semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03240251A true JPH03240251A (en) | 1991-10-25 |
Family
ID=12501160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9037569A Pending JPH03240251A (en) | 1990-02-19 | 1990-02-19 | Method of repairing defective semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03240251A (en) |
-
1990
- 1990-02-19 JP JP9037569A patent/JPH03240251A/en active Pending
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