JPH03227530A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a decrease in an effective barrier height due to a tunneling current and a Schottky effect by providing a second semiconductor layer laminated reversely to a first semiconductor layer, and providing an insulating layer or a gate electrode for causing a tensile stress at the first and second layers. CONSTITUTION:A [111] laminated GaAs layer 21 (first semiconductor layer) is formed on a substrate 11, a [1'1'1'] laminated GaAs layer 41 (second semiconductor layer) is formed thereon, and a gate electrode 61 is further formed. In this case, a condition in which tensile stresses are generated as indicated by arrows 71-a, 71-b at the end of a gate electrode is selected as sputtering condition of the gate electrode. Thereafter, for example, it is selectively coated with AuGa and Ni, heat treated to be alloyed to form ohmic source and drain electrodes 81, 91. In this case, a reverse piezoelectric polar electrodes are generated as indicated by arrows 101, 111 by a tensile stress 17 with a Ge intermediate layer 31 as a boundary. Thus, a decrease in an effective barrier height due to a tunneling current and a Schottky effect can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor used in high speed logic circuits, high frequency amplifiers, etc., and a method for manufacturing the same.

[Conventional technology]

Field effect transistor using ■-■ group compound semiconductor (
FET) is being developed and put into practical use as a basic element for high-speed logic circuits, high-frequency amplifiers, etc.

Among them, GaAsME8FET is the most advanced in development. In integrating such MESFETs, it is necessary to improve mutual conductance, which represents current drive capability, and to improve forward breakdown voltage of the gate to ensure a sufficient noise margin.

Shortening the gate length is effective for improving the performance of MESFETs. In order to suppress the short channel effect and improve performance, efforts have been made to make the channel highly concentrated and thin and to prevent carriers from seeping out from the channel. For example, IEEE Transaction on Electron Devices, Inc. (IEEE Transaction
on Electron Devjces), Volume 32,
2314 (1985). Among these, M
It has been shown that the leakage of carriers toward the substrate can be suppressed using piezoelectric polarization induced by stress in the insulating film covering the ESFET.

That is, as shown in FIG.
In the ESFET in which the 8 s 02 film 140 is deposited on the surface, the figure of merit shows that the dependence of the threshold voltage Vth on the gate length changes favorably depending on the thickness of the 8 s 02 film. Here, K=8μW/2dL and l
), ε is the dielectric constant of the substrate 10 (substrate in GaAs (100)), electron mobility in the μdn type channel 50, d is the effective thickness of the channel, W is the gate width, and L is the gate length.

On the other hand, when the channel is made highly doped, the electric field strength at the surface increases because a gate junction is formed directly in the highly doped layer, resulting in an increase in the Schottky effect and tunnel current. These cause a reduction in the effective barrier hide and reduce the noise margin. The noise margin must be increased in proportion to the degree of integration, and should be as high as possible in terms of design. A known method is to introduce a lightly doped layer or a non-doped layer between the gate electrode and the channel in order to prevent the effective reduction of the gate.

Also, we are Ga As M E 8 F E T
When manufactured on a (111) substrate, the magnitude of piezoelectric polarization, which is effective in suppressing seepage, is constant in all gate directions, as reported in, for example, Technical Digest on 1988 International Journal.・Electron Devices Meeting f (Tech-nic
al Digests of 1988 Intern
ational ElectronDevices M
(eating) reported on page 846. Therefore, (1
11) It is known that the substrate is advantageous in obtaining constant piezoelectric polarization for all gate directions.

[Problem to be solved by the invention]

Countermeasures such as those described in the prior art are known to deal with the increase in carrier seepage from the channel due to the increase in the concentration of the channel, but these are not sufficient to improve the degree of integration. Therefore, there is a need for a method that simultaneously prevents the carrier from seeping out and effectively prevents the reduction of the barrier hide. An object of the present invention is to provide a field effect transistor that can suppress the deterioration of device characteristics due to the high concentration of the channel described above. Further, it is an object of the method for manufacturing a field effect transistor of the present invention to provide a manufacturing method that can easily and stably manufacture such a field effect transistor.

[Failure to solve the problem]

The field effect transistor of the first invention of the present application has a first structure in which a group III atomic layer and a group III atomic layer of a group III compound semiconductor constituting a zincblende crystal are laminated in the [111] axis direction on a substrate. a semiconductor layer, and a second semiconductor layer stacked on the first semiconductor layer in a direction opposite to the first semiconductor layer, and an insulating film or a gate that generates tensile stress in the first and second semiconductor layers. comprising an electrode, an n-type channel at and near the interface between the first and second semiconductor layers, and a source electrode and a drain electrode electrically connected to the n-type channel. It is.

In addition, the field effect transistor of the second invention of the present application has a structure in which a group atomic layer and a layer atomic group atomic layer of a group ■-■ group compound semiconductor constituting a zincblende crystal are laminated in the (111) axis direction on a substrate. an insulating film that provides a first semiconductor layer and a second semiconductor layer stacked on the first semiconductor layer in the opposite direction to the first semiconductor layer, and that generates compressive stress in the first and second semiconductors; comprising a gate electrode, an n-type channel at and near the interface between the first and second semiconductor layers, and a source electrode and a drain electrode electrically connected to the nfjl channel. It is.

In addition, the field effect transistor of the third invention of the present application is a field effect transistor in which a group atomic layer and a layer atomic layer of a group ■ of a group ■-■ compound semiconductor constituting a zincblende crystal are laminated in the (111) axis direction on a substrate. a second semiconductor layer stacked on the first semiconductor layer in the opposite direction to the first semiconductor layer; an insulating film or gate that generates compressive stress in the first and second semiconductors; A book comprising an electrode, a p-type channel at and near the interface between the first and second semiconductor layers, and a source electrode and a drain electrode electrically connected to the p-type channel. It is.

Further, in the field effect transistor of the fourth invention of the present application, a group ■ atomic layer and a group ■ atomic layer of a ■-■ group compound semiconductor having polarized zincblende crystals are laminated in the [IT] axis direction on a substrate. and a second semiconductor layer laminated in the opposite direction to the first semiconductor layer on the first semiconductor layer, and an insulator that generates tensile stress in the first and second semiconductors. comprising a film or a gate electrode, a p-type channel at and near the interface between the first and second semiconductor layers, and a source electrode and a drain electrode electrically connected to the p-type channel. It is characterized by:

Further, the method for manufacturing a field effect transistor according to the fifth invention of the present application is such that the group atomic layer and the group atomic layer of the atomic group vol. (111) forming a first semiconductor layer by laminating them in the axial direction; laminating at least one group (III) atomic layer on the first semiconductor layer; forming a second semiconductor layer by stacking the first and second semiconductor layers in the opposite direction; and introducing impurities into the interface and vicinity of the first and second semiconductor layers to form an n-type channel or a p-type semiconductor layer.
and forming an insulating film or a gate electrode on the second semiconductor layer that generates tensile stress or compressive stress in the first and second semiconductor layers. It is.

[Effect]

In the present invention, the FET is operated based on the piezoelectric effect under a certain stress.
The polarization that occurs in the channel of is constant regardless of the gate direction in the (111) plane of the zincblende type ■-■ group compound semiconductor.
It is effective to confine carriers in the channel by using the inherent property of the crystal that the polarity is reversed between the (111) plane and the (111) plane, and by a structural device that reverses the stacking direction of the crystal by sandwiching the channel. In the field effect transistor of the first invention of the present application, piezoelectric polarization generated in the [111] laminated crystal due to tensile stress from the substrate side across the n-type channel, and piezoelectric polarization generated in the [111] laminated crystal from the gate electrode side. The piezoelectric polarization in the opposite direction increases the electron confinement effect in the channel, and the piezoelectric polarization on the gate electrode side increases the effective barrier thickness, resulting in an effective barrier hydration due to tunneling current and Schottky effect. This prevents a decline in

In addition, in the field effect transistor of the second invention of the present application, piezoelectric polarization generated in the (111) laminated crystal due to compressive stress is observed from the substrate side sandwiching the n-type channel, and piezoelectric polarization is generated in the (111) laminated crystal from the gate electrode side. The opposite piezoelectric polarization generated in the gate electrode increases the electron confinement effect in the channel, and the piezoelectric polarization on the gate electrode side increases the effective barrier thickness, increasing the effective barrier thickness due to tunneling current and Schottky effect. Prevents the decline of Paliano Ito.

In addition, in the field effect transistor of the third invention of the present application, piezoelectric polarization generated in the [111] laminated crystal due to compressive stress from the substrate side with the p-type channel metal sandwiched, and piezoelectric polarization generated in the [111] laminated crystal from the gate electrode side. The piezoelectric polarization in the opposite direction that occurs in the gate electrode increases the hole confinement effect in the channel, and the piezoelectric polarization on the gate electrode side increases the effective barrier thickness, increasing the effective barrier thickness due to tunneling current and Schottky effect. Prevents barrier hide from decreasing.

In addition, in the field effect transistor of the fourth invention of the present application, piezoelectric polarization generated in the (111) laminated layer 1 due to tensile stress from the substrate side in the p-type channel ta, and (111) laminated crystal from the gate electrode side. The piezoelectric polarization in the opposite direction increases the hole confinement effect in the channel, and the piezoelectric polarization on the gate electrode side increases the effective barrier thickness, increasing the effective barrier thickness due to tunneling current and Schottky effect. Prevents the deterioration of barrier hide.

Furthermore, in the method for manufacturing a field effect transistor according to the fourth invention of the present application, a crystal structure in which the crystal lamination direction in the field effect transistor of the present invention is reversed constitutes a non-polar semiconductor.
Since the interlayer is used, crystal growth properties that can be produced easily and stably work effectively in production.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows GaAsME8F, which is an embodiment of the first invention of the present application.
It is a sectional view showing ET. On a semi-insulating GaAs (111) A-plane substrate (substrate 11) maintained at a temperature of 550 t, one atomic layer of Ga and As are alternately deposited in the order of molecular beam epitaxy to form a (111) stacked GaAs.
A layer 21 (first semiconductor layer) is grown to a thickness of 500 nm and terminated with a layer S. A Ge intermediate layer 31 consisting of a Ge47) 3 atomic layer is continuously grown thereon, and then A s t
A (111) stacked GaAs layer 41 (second semiconductor layer) is grown to a thickness of 3 Q nm by alternately depositing one atomic layer at a time in the order of Ga by molecular beam epitaxy. Note that 10 nm from the top of the (111) stacked GaAs layer 21 and [111
] An n-type channel 51 is formed by doping, for example, 8i over 101 m from the bottom of the laminated GaAs layer 41.

Furthermore, a gel electrode 61 made of the silicone WNx is formed by sputtering and reactive dry etching. At this time, the sputtering conditions (substrate temperature, gas pressure, sputtering power) for the gate electrode are indicated by arrows 71-a and 71 at the end of the gate electrode.
- Select the conditions under which tensile stress occurs as shown in b. For example, a 1WNx film is formed by DC sputtering in a mixed gas of argon and nitrogen (pressure: 80 mTorr) with a nitrogen partial pressure ratio of 0.05 and applying a sputtering power of 300 W. Since the WNxll formed in this way has a coefficient of thermal expansion larger than GaA s, the above-mentioned tensile stress (!l stress) occurs when it is cooled to room temperature.
UGe and Ni are selectively deposited and an alloying heat treatment is performed to form an ohmic source electrode 81 and a drain electrode 91 to complete the process. At this time, G by the tensile response cuff 1
Piezoelectric polarization occurs in mutually opposite directions as shown by arrows 101 and 111 with the e-intermediate 431 as a boundary.

Although an embodiment of the method for manufacturing a field effect transistor of the present invention, which is easy to develop and manufacture, has been shown here, it is also possible to manufacture the field effect transistor without depositing an intermediate layer. This is also common to the second, third, and fourth inventions of the present application described below. In addition, the intermediate layer is thin enough to contain Ge, which is lattice-matched to GaAs.
In addition, we also specialize in Si and other materials.

FIG. 2 is a schematic diagram showing the appearance of a band under the gate electrode in an embodiment of the first invention of the present application.

The conduction band edge C21 is the (111) stacked layer G a A on the surface side.
As shown by the arrow 110, the piezoelectric polarization of the s layer 41 is n
Piezoelectric polarization on the underside of mold channel 51 (indicated by arrow 111)
Since the piezoelectric polarization is the same at the top and bottom of the n-type channel (in the direction shown by arrow 111), as shown in the figure,
In other words, it is higher than the conduction band edge C1l of (31.41 replaced with (111) stacked GaAs layer)
The effective barrier layer thickness will increase. Note that the valence band edge V21 is also higher than the valence band edge Vll, similar to the conduction band edge. Therefore, the effect of confining electrons in the n-type channel increases.

FIG. 3 shows the G a A sM of an embodiment of the second invention of the present application.
It is a sectional view showing E8FET.

Semi-insulating GaAs (111) maintained at a temperature of 550°C
On the B-plane substrate (substrate 12), one atomic layer of As and Ga are deposited alternately in the order of molecular beam epitaxy (111
) Laminated GaAs layer 22 (first f) semiconductor m) 59Q
grow by nm. A Ge intermediate layer 32 consisting of three atomic layers of Ge is successively grown thereon, and then Ga and As are alternately deposited one atomic layer at a time in that order (111) to form a laminated GaAs layer 42 (second) semiconductor. layer) is grown to a thickness of 30 nm. In addition,(
111) For example, Si is doped to form an n-type channel 52 for 1Q nm from the top of the (111) stacked GaAs s layer 22 and 1Q nm from the bottom of the (111) stacked GaAs s layer 42. Furthermore, a gate electrode 62 made of WNx is formed by sputtering and reactive dry etching.

At this time, an arrow 72-a is shown at the end of the gate electrode as sputtering conditions (gas pressure, sputtering power) for the gate electrode.

Select conditions under which compressive stress occurs as shown in 72-b. For example, in a mixed gas of argon and nitrogen with a nitrogen partial pressure ratio of 0.05 (pressure 40 m Torr), 150 W
A WNx film is formed by direct current sputtering by applying a sputtering power of . Since the WNx film thus formed has a coefficient of thermal expansion smaller than GaAs, the above-mentioned compressive stress occurs when the film is cooled to room temperature. Then, for example, AuGe and Ni
is selectively deposited and subjected to an alloying heat treatment to form an ohmic source electrode 83 and a drain electrode 93, thereby completing the process. At this time, due to the compressive stress, piezoelectric polarization occurs in mutually opposite directions as shown by arrows 112 and 102 with the Ge intermediate layer 33 as a boundary.

The appearance of the band under the gate electrode in this embodiment is as shown in FIG. 2, similar to the embodiment of the first invention of the present application, and the thickness of the barrier is increased.

FIG. 4 is a sectional view showing a MESFET according to an embodiment of the third invention of the present application.

On a semi-insulating GaAs (111) A-plane substrate (substrate 13) maintained at a temperature of 550° C., Ga and As are alternately deposited in that order by molecular beam epitaxy to form a (111) laminated GaAs layer 23 (first semiconductor layer). layer) to a thickness of 500 nm. A Ge intermediate layer 33 consisting of three atomic layers of GeA is successively grown thereon, and then As and [[ group elements (AJ, Ga) are deposited in this order to form a stacked layer A! An α3Ga0,7As layer 43 (second semiconductor layer) is grown to a thickness of 20 nm. In addition,(
111) A p-type channel 53 is formed by doping, for example, Be over 15 nm from the upper end of the laminated GaAs layer 23. Furthermore, a gate electrode 63 made of F) WNx is formed by sputtering and reactive dry etching. At this time, arrows 73-a and 73-1 are placed at the end of the gate electrode as sputtering conditions (gas pressure, sputtering power) for the gate electrode.
) Select the conditions under which compressive stress occurs. For example, a mixed gas of argon and nitrogen with a nitrogen partial pressure ratio of 0.05 (pressure 4
1) A WNx film is formed by DC sputtering at a temperature of 0 mTorr with a sputtering power of 15 owo applied.

Thereafter, for example, AuZn and Ni are selectively deposited and an alloying heat treatment is performed to form an ohmic source electrode 84 and a drain electrode 94, thereby completing the structure. At this time, arrow 73-a
, 73-b causes piezoelectric polarizations shown by arrows 103 and 113 in opposite directions with the Ge intermediate layer 34 as a boundary.

FIG. 5 is a schematic diagram showing the state of the band under the gate electrode of this example. The valence band edge V23 is the [111) laminated AI' 0.30a 0.7As layer 4 on the surface side.
As shown by arrow 103, the piezoelectric polarization of 3 is opposite to the piezoelectric polarization on the lower side of p-type channel 53 (indicated by arrow 113), so that piezoelectric polarization is caused above and below the p-type channel 53 as shown. are the same (direction shown by arrow 113) (that is, 33, 43 are (111) laminated Aj!, 3Ga5.7
The effective barrier layer thickness is higher than that of the valence band edge V13 (replaced with an As layer), and the effective barrier layer thickness is increased. The conduction band edge C23 is also higher than the conduction band edge C13, similar to the valence band edge. Moreover, compared to the one shown in FIG. 1, carrier seepage is reduced due to the heterojunction.

FIG. 6 is a sectional view showing a MESFET according to an embodiment of the fourth invention of the present application.

On a semi-insulating (faAs (111) B-plane substrate (substrate 14) at a temperature of 550 t'', As and Ga are alternately deposited in that order by molecular beam epitaxy to form a [111] laminated GaAs layer 24.
Grow 5QQnm. On top of this, a Ge intermediate layer 34 consisting of three atomic layers of Ge is continuously grown, and then a group Ⅰ element (A
[111
] Laminated AI O, 3GaO, 7As layer 44 with a thickness of 20 nmF
y, lengthen. In addition, (111) stacked GaAs layer 2.4
A p-type channel 54 is formed by doping, for example, Be with 15 nm from the upper end. Furthermore, a gate electrode 64 made of F) WNx is formed by sputtering and reactive dry etching. At this time, as the sputtering conditions (gas pressure, sputtering power) for the gate electrode, conditions are selected that generate tensile stress at the ends of the gate electrode as shown by arrows 74-a and 74-b. For example, a WNx film is formed by direct current sputtering in a mixed gas of argon and nitrogen (pressure: 80 mTorr) with a nitrogen partial pressure ratio α05 and a sputtering power of 300 W applied. Then, for example, AuZn and N
Then, an ohmic source electrode 84 and a drain electrode 94 are formed by selectively depositing the oxide and performing an alloying heat treatment. At this time, due to the tensile stress, piezoelectric polarization occurs in mutually opposite directions as shown by arrows 104 and 114 with the Ge intermediate layer 34 as a boundary.

Similar to the third invention, the appearance of the band below the gate electrode remains as shown in FIG. 5, and the thickness of the barrier increases. or,
Compared to the one shown in FIG. 3, carrier oozing is reduced due to the use of a heterojunction.

Although we have described an example of applying stress to the gate electrode above, it is also possible to generate compressive stress or tensile stress by depositing an insulating film such as an 8i0□ film on the surface, as shown in Figure 7. I can do it. Example 11, sio
□For the film, α1μm SiO□ is produced using low-pressure chemical vapor deposition method.
After forming the film, 1 layer is further deposited using plasma chemical vapor deposition method.
When 8i02 film of μm is formed, 3~5X10 dy
A compressive stress of ne/csL can be generated.

Furthermore, when a SiO□ film with a thickness of 1 μm is formed by atmospheric pressure chemical vapor deposition, a tensile stress of 1×10 dyne/cm can be generated.

Although the above description has been made using a GaAs-based MESFET as an example, the aA of the present invention is also applicable to a 9FET using a zinc blende compound semiconductor such as InP, which is not limited to an LfaAs-based MESFET.

〔Effect of the invention〕

As explained above, in the field effect transistor of the first invention of the present application, for example, in the case shown in the embodiment of the present invention, the (111) stacked G a The electron confinement effect in the channel increases due to the piezoelectric polarization generated during s and the piezoelectric polarization in the opposite direction generated in the [111] stacked GaAs s from the gate electrode side, and furthermore, due to the piezoelectric polarization on the gate electrode side, The effective barrier thickness increases, which has the effect of preventing a decrease in the effective barrier hide due to tunnel current and Schottky effect. In order to improve the degree of integration, this makes it possible to prevent the short channel effect from increasing due to the increase in carrier seepage due to short channels, increase the current drive capability, and reduce the noise margin. It has the effect of suppressing

In addition, in the field effect transistor of the second invention of the present application, for example, in the case shown in the embodiment of the present invention, a piezoelectric current generated in the (111) stacked GaAs from the substrate side due to compressive stress across the n-type channel. Polarization and piezoelectric polarization in the opposite direction generated in the (111) stacked Ga As from the gate electrode side increases the electron confinement effect in the channel, and furthermore, the piezoelectric polarization on the gate electrode side increases the effective barrier This increases the thickness of the barrier layer, which has the effect of preventing a decrease in the effective barrier hydride due to tunnel current and the Schottky effect.

Similar to the field effect transistor of the first invention of the present application, in order to improve the degree of integration, this prevents an increase in the short channel effect due to an increase in carrier seepage due to short channels, and increases the current drive capability. This has the effect of suppressing deterioration of the noise margin.

In addition, in the third field effect transistor of the present application, for example, in the case shown in the embodiment, the piezoelectric polarization generated in the (111) stacked GaAs from the substrate side due to compressive stress across the p-type channel, and the gate electrode From the side, the piezoelectric polarization in the opposite direction that occurs in the (111) stacked AjxGa+-xAs increases the hole confinement effect in the channel, and furthermore, the piezoelectric polarization on the gate electrode side increases the effective barrier thickness. However, it has the effect of preventing a decrease in the effective barrier hydride due to tunnel current and the Schottky effect. In order to improve the degree of integration, this makes it possible to prevent the short channel effect from increasing due to the increase in carrier seepage due to short channels, increase the current drive capability, and reduce the noise margin. It has the effect of suppressing

Further, in the field effect transistor of the fourth invention of the present application, for example, in the case shown in the embodiment, [111] laminated G
The piezoelectric polarization generated during aA s and from the gate electrode side (
111) The piezoelectric polarization in the opposite direction that occurs in the stacked A/xGat-xAs increases the hole confinement effect in the channel, and furthermore, the piezoelectric polarization on the gate electrode side increases the effective barrier thickness. This has the effect of preventing a decrease in the effective barrier hydride due to tunnel current and the Schottky effect. In order to improve the degree of integration, this makes it possible to prevent the short channel effect from increasing due to the increase in carrier seepage due to short channels, increase the current drive capability, and reduce the noise margin. It has the effect of suppressing

Further, according to the method for manufacturing a field effect transistor of the present invention, crystals in which the crystal stacking direction is reversed in the field effect transistor of the present invention having the above-mentioned effects can be manufactured by using a group interlayer constituting a nonpolar semiconductor. It has the advantage that it can be easily and stably manufactured.

The present invention described above has G a
It is effective not only in the case of As, but also has a wide range of applications in field effect transistors using all zinc blende type ■-■ group compound semiconductors such as InP.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the first invention of the present application, and FIG.
The figure is a schematic diagram showing the band structure of the embodiment shown in Fig. 1, Fig. 3 is a sectional view showing an embodiment of the second invention of the present application, and Fig. 4 shows an embodiment of the third invention of the present application. 5 is a schematic diagram showing the band structure of the embodiment shown in FIG. 4, FIG. 6 is a sectional view showing an embodiment of the fourth invention of the present application, and FIG. 7 is a sectional view showing a conventional example. It is a diagram. 10-14...Substrate, 21, 42, 23...(11
1) Laminated GaAs layer, 31, 32, 33, 34 = -G
e intermediate layer, 41.22-(TTT”l stacked GaAs layer,
4a-(Tri) Laminated AI 6.30 a 6.1
A s layer, 44...-(111) laminated Aj, 3G a
o, 7A s layer, 50, 51.53-n type channel, 5
2.54...p-type channel, 60, 61, 62, 63
．． 64... Gate electrode, 71-a, 71-b, 74-
a, 74-b ---arrow indicating tensile stress, 72-
a, 72-b, 73-a. 73-b...arrow indicating compressive stress, 80, 81, 82
, 83° 84...source electrode, 90, 91, 92, 9
3.94...Drain electrode, 120...Meter-shaped drain region, 130...N-type drain region, 140-...
S t Oz film, C11°C21, C13, C23...
・Conduction band edge, Vll, V21. V13°V23...Valence band edge.

Claims (1)

[Claims] 1. A first semiconductor layer in which a group III atomic layer and a group V atomic layer of a III-V group compound semiconductor constituting a zincblende crystal are laminated in the [111] axis direction on a substrate; A second semiconductor layer is provided on the first semiconductor layer in a direction opposite to the first semiconductor layer, and an insulating film or a gate electrode is provided that generates tensile stress in the first and second semiconductor layers, An electric field characterized by having an n-type channel at and near the interface between the first and second semiconductor layers, and having a source electrode and a drain electrode electrically connected to the n-type channel. effect transistor. 2. A first semiconductor layer in which a group III atomic layer and a group V atomic layer of a group III-V compound semiconductor constituting a zincblende crystal are laminated in the [111] axis direction on a substrate, and the first semiconductor layer A second semiconductor layer stacked in the opposite direction to the first semiconductor layer is provided thereon, an insulating film or a gate electrode is provided that produces compressive stress on the first and second semiconductor layers, and A field effect transistor comprising an n-type channel at and near an interface between semiconductor layers, and a source electrode and a drain electrode electrically connected to the n-type channel. 3. A first semiconductor layer in which a group III atomic layer and a group V atomic layer of a III-V group compound semiconductor constituting a zincblende crystal are laminated in the [111] axis direction on a substrate, and the first semiconductor layer. A second semiconductor layer stacked in the opposite direction to the first semiconductor layer is provided thereon, an insulating film or a gate electrode is provided that produces compressive stress on the first and second semiconductor layers, and A field effect transistor comprising a p-type channel at and near an interface between semiconductor layers, and a source electrode and a drain electrode electrically connected to the p-type channel. 4 A group III atomic layer and a group V atomic layer of a III-V group compound semiconductor constituting a zincblende crystal are placed on a substrate [@1@@1@
@1@] A first semiconductor layer laminated in the axial direction, and a second semiconductor layer laminated in the opposite direction to the first semiconductor layer on the first semiconductor layer, a source comprising an insulating film or a gate electrode that produces tensile stress in the semiconductor, a p-type channel at and near the interface between the first and second semiconductor layers, and electrically connected to the p-type channel; A field effect transistor comprising an electrode and a drain electrode. 5 A first semiconductor layer is formed by laminating a group III atomic layer and a group V atomic layer of a III-V group compound semiconductor constituting a zincblende crystal on a substrate in the [111] axis direction or in the [111] axis direction. a step of laminating at least one group IV atomic layer on the first semiconductor layer; and a step of laminating at least one group IV atomic layer on the group IV atomic layer in the opposite direction to the first semiconductor layer. forming a semiconductor layer; forming an n-type channel or a p-type channel by introducing impurities into and near the interface between the first and second semiconductor layers; and forming a semiconductor layer on the second semiconductor layer. 1. A method for manufacturing a field effect transistor, comprising at least the step of forming an insulating film or a gate electrode that generates tensile stress or compressive stress in the first and second semiconductor layers.