JPH03222364A - Electrostatic induction semiconductor device - Google Patents

Abstract

PURPOSE:To improve an electrostatic induction semiconductor device in rise and fall time in an OFF-operation so as to make it retain a low ON-voltage characteristic by a method wherein a cathode and an anode region are provided onto the surface of a semiconductor substrate, and a low resistive region is formed along a gate region buried in the semiconductor substrate coming into direct contact with the gate region. CONSTITUTION:In a buried-gate type electrostatic induction semiconductor device, a low resistive region 8 is formed along a gate region 12 coming into direct contact with it inside semiconductor substrate 1. In addition, the low resistive region 8 is formed of doped polysilicon highly doped with impurity of the same conductivity type as that of the gate region 12 and constituted in such a manner that impurity contained in an impurity diffusion layer used for the gate region 12 is made to diffuse from the doped polysilicon. As a chip is very small in gate resistance through all the surface, a signal applied to a gate electrode 23 is directly and equally transmitted to all the gate region 12, in result the electrostatic semiconductor device of this design can be improved in speed characteristics of rise and fall, and an overcurrent is prevented from concentrating locally in a transient state and the semiconductor device can be fully protected against damage.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an electrostatic induction semiconductor device.

[Conventional technology]

As an electrostatic induction semiconductor device, there is a buried gate type electrostatic induction cell shown in FIG.

This electrostatic induction silice includes a cathode region (n" region) 81 on one side of a semiconductor substrate 80, an anode region (p" region) 82 on the other surface, and a gate region ( It is equipped with a p゛ region 85,
Further, high resistivity regions (low impurity concentration regions) 83 and 84 are provided between the cathode region 81 and the anode region 82 . The high resistivity region 84 is a so-called Heas region, and the high resistivity region 83 is for improving the efficiency of injection of holes from the anode and the efficiency of injection of electrons from the cathode. Then, in the cathode region 81, a cathode electrode K is provided.
An anode electrode A is provided in the anode region 82 , and an anode electrode A is provided in the anode region 82 .
5 is provided with a gate electrode G, respectively.

In this electrostatic induction silice, a signal is applied to the gate electrode G to adjust the height of the potential barrier formed between the gate region 85, thereby controlling the current flowing between the cathode and the anode. .

[Problems to be Solved by the Invention] However, this electrostatic induction silicate has a problem in that the rising and falling speeds during on/off operations are slow. As shown in FIG.
5 is composed of a p impurity diffusion region, and in a part of the gate region far from the gate electrode G, a relatively high resistance exists between the gate electrode G and a signal to the gate electrode G. This is because it takes a considerable amount of time after the signal is applied until the signal is actually transmitted to a portion of the gate region 85 that is remote from the gate electrode G. In particular, in the case of a current rise operation, there is a risk that an overcurrent will occur and damage the electrostatic induction shield.

The fifth gate region 85 is formed on the surface of the semiconductor substrate 81.
In the surface gate type electrostatic induction silice shown in the figure, the signal applied to the gate electrode G is transmitted to the entire gate region 85 without delay, so the problem of slow rise and fall speeds during on/off operation is improved. Ru. However, this surface-gate type electrostatic induction thyristor has another problem in that the on-voltage is high because the contact area between the cathode region 81 and the cathode electrode is small.

In view of the above circumstances, an object of the present invention is to provide a buried gate type electrostatic induction sink that has improved rise/fall delay during off-operation and maintains low on-voltage characteristics. .

[Means to solve the problem]

In order to solve the above problem, the buried gate type static induction semiconductor device according to claim 1.2 includes a semiconductor substrate in which a low resistance region in direct contact with the gate region is formed along the gate region. We are trying to adopt a configuration that is formed by

In addition, in the buried gate type electrostatic induction semiconductor device according to claim 2, the low resistance region is made of doped polysilicon doped with impurities of the same conductivity type as the gate region at a high concentration, and the impurity diffusion for the gate region is provided. The structure is such that impurities in the layer are diffused from the doped polysilicon.

The electrostatic induction semiconductor device of the present invention is not limited to a thyristor configuration but also includes a transistor configuration. However, in the case of a transistor, the cathode is commonly called the source and the anode is commonly called the drain, so in the case of a transistor, the cathode in the claims should be read as the source and the anode as the train.

The electrostatic induction semiconductor device of the present invention is not limited to a vertical structure in which a cathode region and an anode region are formed on one side and the other surface of a semiconductor substrate, but also a horizontal structure in which a cathode region and an anode region are formed on the same surface of a semiconductor substrate. It can also be a structure.

Materials for the low resistance region in contact with the gate region include refractory metals (eg, tungsten), doped polysilicon, and the like.

[For production]

In the buried gate type static induction semiconductor device of this invention,
A low resistance region that is in direct contact with the gate region is provided along the gate region, eliminating the conventional situation in which high resistance exists between the gate electrode and the gate electrode even at locations far from the gate electrode. Resistance is extremely low across the entire chip.

Therefore, the signal applied to the gate electrode is immediately and equally transmitted to the entire gate region, eliminating variations in the voltage applied to the gate junction, variations in gate trigger characteristics, and deviations in the tie for pulling out the carrier from the gate during off-operation. Since both of these are reduced, the rise and fall speed characteristics are improved (for example, the critical on-current increase rate d i / d t becomes higher), and at the same time, local overcurrent concentration in transient conditions is reduced. There is no need to worry about device destruction.

[Embodiments] Hereinafter, embodiments of the electrostatic induction semiconductor device according to the present invention will be described in detail from the manufacturing stage.

Example 1 First, as shown in FIG. 1(a), an anode region (p.
An oxide film 4 is formed by thermal oxidation treatment on the surface of a silicon semiconductor substrate 1 in which a high resistivity region (n- region) 3 is laminated on a region) 2.
form.

Then, as shown in FIG. 1(b), a portion of the oxide film 4 corresponding to a portion where a gate region is to be formed is selectively etched to open a window 5, and then, using the windowed oxide film 4 as a mask, the first As shown in Figure (C), an anisotropic etching process is applied to the silicon semiconductor substrate l, and the etching (
groove) 6 is formed. An n- region is exposed on the inner surface of the recess 6, and p-type impurities are pre-deposited (or ion-implanted) at a high concentration on this exposed surface, as shown in FIG. A shallow p'' region 7 is formed.

When forming the p'' region 7, an extremely thin oxide film is formed on the inner surface of the recess 6, but this is removed by slide etching with hydrofluoric acid, etc., and then etched using the reduction reaction of silane. As shown in FIG. 1 (el), the depression 6 is selectively filled with tungsten by the CVD method to form a low resistance region 8.

After the low resistance region 8, as shown in Figure 1(f),
An oxide film 4 is deposited on the entire surface of the semiconductor substrate 1 by the CVD method, and then an oxide film 4 is deposited on the semiconductor substrate 1, as shown in FIG.
．． 10 is removed by etching leaving only the peripheral portion of the low resistance region 8. The selectively left oxide film portion is the insulating region 1 covering the non-contact area of the gate region in the low resistance region 8.
It is 1.

Next, as shown in Figure 1 (h), a high resistance n layer 3' is formed.
are layered using epitaxial growth method, and then the first
As shown in the figure (+1), a low-resistance n+ layer 13' for the cathode region is laminated using an epitaxial growth method.The impurities in the p'' region 7 are diffused by the heat treatment in these two epitaxial steps, and the gate region 12 is However, since the impurity may be diffused too deeply and the concentration gradient at the junction of the gate region 12 becomes low, in order to make the concentration gradient at the junction of the gate region 12 steep, It is desirable to epitaxially grow the n-layer 3' of the resistor by a low-temperature growth method using optical excitation, etc. If the concentration gradient at the junction is steep, the spread of the depletion layer in the gate region becomes small. , the space between the gate regions can be widened,
It becomes possible to further lower the on-voltage.

Next, as shown in FIG. 1 (jl), the n-layer 3' and the like are selectively etched so that the insulating region 11 is exposed at the gate pad portion at the right end of the illustrated semiconductor substrate 1. As shown in FIG. 1(k), an oxide film (SiOx film) 15 is again laminated on the semiconductor substrate 1 by the CVD method.

After this, as shown in FIG. 1 (11), the contact window 18 for the cathode electrode and the contact window 19 for the gate electrode are
Open the day.

Then, as shown in FIG. 1(b), the gate electrode 23
, forming the cathode electrode 24 and the anode electrode 2
2 and completed a buried gate type electrostatic induction silice.

In the completed buried gate type electrostatic induction silicon risk, a low resistance region 8 that is in direct contact with the gate region 12 is provided along the gate region 12 in the semiconductor substrate 1 . The non-contact area of the gate region in the low resistance region 8 is covered with an insulating region 11 to provide necessary electrical insulation from the high resistivity region 3. The gate regions 12 extend in a direction perpendicular to the plane of the paper and are connected at locations not shown. As described above, due to the presence of the low resistance region 8, the gate resistance is low throughout.

Example 2 Next, the electrostatic induction risk of Example 2 will be explained.

First, as shown in FIGS. 2(a) to 2(C), recesses (a) 6 are formed in the same manner as in Example 1.

Then, as shown in FIG. 2 fdl, a doped polysilicon layer 40' doped with a high concentration of P-type impurity is formed on the semiconductor substrate l so that the trench 6 is filled. Subsequently, the doped polysilicon layer 40' is removed using a normal planarization etching method, leaving only the portion filled in the trench 6, as shown in FIG. 2(e).
As shown in FIG. 2, a low resistance region 40 is formed.

Next, as shown in FIG.
As shown in FIG. 2(g), the oxide film 4.41 is removed by etching leaving only the area around the low resistance region 40. The selectively left oxide film portion is an insulating region 42 that covers the non-contact area of the gate region in the low resistance region 40. After this, as shown in FIG. 2(h), the high resistance n-layer 3
' are stacked using epitaxial growth. By the heat treatment in this epitaxial process, a part of the p-type impurity doped in the low resistance region 8 is diffused (autotoped), and a gate region 12 is formed as shown in FIG. 2 (hl). .

After this, an electrostatic induction thyristor is obtained by going through the same steps as in FIG. , a low resistance region 40 made of doped polysilicon is provided in place of the low resistance region 8 made of tungsten, and the p-type impurity in the gate region 12 is diffused from the low resistance region 40. Example 1
It is only different from the thyristor obtained in .

This invention is not limited to the above embodiments. For example, another embodiment may be one in which the p-type and n-type in FIG. 1 or 2 are reversed.

Furthermore, the material and method for forming the low resistance region may be other than those exemplified above.

〔Effect of the invention〕

Since the buried gate type electrostatic induction semiconductor device according to the present invention is of the buried gate type, low on-voltage characteristics are maintained, and the gate resistance is low throughout the device due to the low resistance region without being affected by the distance from the gate electrode. This improves the delay in rising and falling during on/off operation.

[Brief explanation of drawings]

Claims (1)

[Claims] 1. In an electrostatic induction semiconductor device including a cathode region and an anode region on the surface of a semiconductor substrate and a gate region embedded in the semiconductor substrate, the gate region has a structure in which the gate region is in direct contact with the cathode region and the anode region. A buried gate electrostatic induction semiconductor device in which a low resistance region is formed along a gate region. 2. A claim in which the low resistance region is made of doped polysilicon heavily doped with impurities of the same conductivity type as the gate region, and the impurity of the impurity diffusion layer for the gate region is diffused from the doped polysilicon. 1. The buried gate electrostatic induction semiconductor device according to 1.