JPH03219724A - Tracking/holding circuit - Google Patents

Abstract

PURPOSE:To make the timing of data acquisition constant without receiving modulation by using a bootstrap circuit to cancel a voltage drop due to a switch ON resistance. CONSTITUTION:PET switches SW2, SW3 are turned on in the tracking mode and a signal with unmagnification and opposite sign to an input signal Vin is outputted as a T/H output. In this case, a current charging a hold capacitor CH flows to the switch SW2 and the drain voltage of the switch SW2 is fluctuated by a voltage drop across its ON-resistance. Since components CH and C1, SW2 and SW5 have respectively the same characteristic, the drain voltage of a SW5 changes similarly to that of the SW2. The drain voltage of the SW5 is shifted by +5V in the circuit 5 and an AC signal around +5V is inputted from the circuit 5 to a FF 6. When the output Q of the FF 6 is logic 'H', the output of the circuit 5 is outputted as it is and a level difference between the gate and drain of the SW2 is constant as 5V. When the output of the FF 6 is logic 'L', a common level is outputted and the level difference between the gate and the drain of the SW2 is constant as 5V. When the output of the FF 6 is logic 'L', a common level is outputted and the SW2 is opened.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to the reduction of distortion of a hold waveform caused by an acquisition timing shift in a track/hold circuit.

<Prior art> Figure 7 shows a conventional track/hold circuit (hereinafter '/H
FIG. 2 is a configuration circuit diagram showing a specific example of a circuit (also referred to as a circuit). 1 is a track/hold amplifier (also called T/H amplifier),
SWl and SW2 are the first .
The second FET" switch, CH is a hold capacitor connected between the output terminal of T/H amplifier 1 and the connection point of FETET switch I and SW2, and R3 is the output of hold capacitor CH and T/H amplifier 1. Damping resistor connected between the terminals, SW3 and SW4 are the 3rd and 4th FET switches connected in series between the inverting input terminal of the T/H angle and the common, 3 is the T/H input voltage V is applied to the input terminal, R1 is a resistor connected between the input terminal n terminal 3 and the connection point of FETET switch 3.SW4, and R2 is the resistance connected between the connection point of SW3.SW4 and T.
/H A resistor connected between the output terminals of the amplifier 1 and having a value equal to R1 (in the case of a gain of 1). 4 is T/H Ang 1
This is the output terminal of this T/H circuit to which the output terminal of is connected.

FET switches SW1 to SW4 are D-MOS FETs
Consists of switches, SW2, 5W3 (7) gate is T
/Hri.

The gates of SWI and SW4 are driven by the inverted clock. These clocks are generated by external circuits.

In track mode, FET switch SW2 SW3
The FETX switches SWI and SW4 are turned off, and the T/8 circuit constitutes an inverting amplifier, and the input voltage ■
in is output with a gain of -1@. In bold mode, FET switches SWI and SW4 are turned on, FET switch SW2. When SW3 is turned off, the voltage value of the inverted output signal at the timing when SW2 is turned off is held in the hold capacitor Cl. In addition, FET switch SW4
is turned on, so the long current due to the T/H input voltage ■io flows to the common and is separated from the T/H output vout.

<Problems to be Solved by the Invention> However, in the above circuit, as the frequency of the input signal voltage V1o increases, the current charging the hold capacitor C1 increases, and the timing for holding due to the voltage drop caused by the on-resistance of the FET switch SW2 increases. was modulated, causing harmonic distortion in the reproduced waveform.

This phenomenon will be explained in detail below. Figure 7'■゛/H
The circuit uses a D-MOS switch for SW2. A D-MOS switch has a capacitance Cgd between the gate and the drain, and the capacitance has voltage dependence.

In other words, as the gate-train voltage V increases, Cg
d also increases. Track (Jd mode) When the frequency of the input signal increases, the current charging the hold capacitor C1 increases, and the voltage drop caused by the on-resistance of SW2 changes.

The gate voltage is constant at, for example, 5cm, but when the train voltage changes due to a voltage drop, v and d change, and therefore Cgd also changes. When Cgd fluctuates due to a change in drain voltage, the CR time constant generated between SW2 and the output resistance of the gate drive circuit changes, and the timing at which SWI is turned off, that is, the timing of data acquisition, is modulated.

The signal waveform that reproduces the data held in this way is the input signal ■. Figure 8 shows this situation, and the waveform of (A) contains harmonic distortion.
) indicates the phase relationship between the input signal V and the current I flowing through the CH in the track n mode.

(B) shows the deviation in acquisition timing, and V
When Qd and Cgd are maximum, the CR time constant is maximum, and the acquisition timing is delayed by Δt1, but
When Vga and Cgd are at the minimum, the CR time constant is at the minimum and the acquisition timing is advanced by Δt2. (C) is the ideal waveform (dotted line two-person waveform) and reproduced waveform (waveform after A/D conversion of 'l'/H circuit output)
It is shown that the reproduced waveform contains harmonic distortion.

The present invention has been made to solve the above problems,
The purpose of this invention is to realize a track/hold circuit in which the timing of data acquisition is constant without being modulated.

Means for Solving the Problem> The track/hold circuit according to the present invention includes at least a track/hold amplifier that performs track operation and hold operation using a common output stage, and one end of which is connected to the output terminal of the track/hold amplifier. and at least a hold capacitor whose other end is connected to the inverting input terminal of the track/hold amplifier during a hold operation, and an FET connected between the other end of this hold capacitor and common.
A switch, a level shift circuit that inputs a voltage corresponding to the voltage at the other end of the hold capacitor, and a drive circuit that turns on the FET switch with a voltage corresponding to the output of the level shift circuit. shall be.

Function> In track mode, the level shift circuit and drive circuit change the potential of the gate terminal of the FET switch to F B
Since the potential changes equal to the potential of the drain terminal of the 'r' switch, the voltage and capacitance between the gate and drain of the FET switch are constant.

Therefore, the timing of data acquisition is also constant.

<Example> Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a configuration circuit diagram showing a first embodiment of the track/hold circuit according to the present invention, which is an inverted type. Here, the same parts as in FIG. 7 are given the same symbols and the explanation is omitted. C1 is a second capacitor whose one end is connected to the output terminal of T/H amplifier 1, and SW5 is a fifth D-MOS for monitoring connected between the other end of capacitor C1 and common.
FET switch, 5 is a level shift circuit that inputs the voltage of the drain terminal of FET switch SW5 and shifts it by 5V, 6 is a level shift circuit that inputs the voltage of the drain terminal of FET switch SW5, and 6 is a 'T' T
This is a D-type flip-flop (A-CMO8) driven by a clock synchronized with an L-level power supply voltage and an H clock (a clock that determines the timing of track mode and hold mode).

The gate of the FET switch SW2 is driven by the output of the flip-flop 6, and the gate of SW5 is always turned on with 5V applied thereto. FE'r switch SW2 and S
W5 and capacitors CH and 01 have the same characteristics.

The operation of the track/hold circuit having the above configuration will now be described. In track mode, FET switch SW2
．． SW3 is turned on and the input signal is output as 1゛/H output.
A signal with the opposite sign and the same size as 1o is output. At this time F
A current I that charges the hold capacitor Co flows through the ET switch SW2, and the drain voltage of the FET switch SW2 fluctuates due to a voltage drop due to its on-resistance (several hundreds of ohms).

Since C1 and C1 and SW2 and SW5 are elements with the same characteristics, the drain voltage of FET switch SW5 is also the same as SW2.
makes exactly the same change. The drain voltage of the FET switch SW5 is shifted by +5V by the level shift circuit 5, and an AC signal centered around +5V is supplied from the level shift circuit 5 to the power supply terminal Vss of the flip flora 16. When the output Q of the flip-flop 6 becomes High due to the clock input synchronized with the T/H clock, the output of the level shift circuit 5 is output as is, so when SW2 is on, the potential difference between the gate and drain of SW2 is always constant at 5V. When the output of the flip-flop circuit 6 is Low, a common level is output and SW2 is turned off. As mentioned above, since the Vgd of the FET switch SW2 is constant in the track moto, the Cgd of the FET switch SW2 is also constant, the CR time constant during switching is also constant, and the data acquisition timing is constant regardless of the input signal.

FIG. 2 shows a first modification of the track/hold circuit shown in FIG. The difference from FIG. 1 is that the output of the level shift circuit 5 is supplied to the power source of the differential switch 7 instead of being supplied to the power source of the flip-flop 16. The output of the D-type flip-flop 6 driven by the tarlock is the switching input of the differential switch 7. Here, a delay corresponding to the switching of the differential switch 6 with respect to the 1'/H clock occurs in the on/off signal of SW2, but this does not become a problem if the overall timing is adjusted. The Q output of circuit 6 and its inverted output are the inverted output of T/H output and T/H, respectively.
By making it an output, the external circuit can be simplified.

FIG. 3 is a second modified example of the track/hold circuit shown in FIG. 1, and is a configuration circuit diagram showing one in which the input of the level shift circuit 5 is taken directly from the drain terminal of SW2. This can be realized if the level shift circuit 5 has an ideal configuration that does not affect the T/H circuit 6, that is, if the input impedance is 2 and the bias current is 0. Capacitor C1
Also, since the FET switch SW5 can be omitted, the circuit becomes simple, and errors due to mismatching between the F B 'I' switches SW2 and SW5 and the capacitors CH and 01 do not occur.

FIG. 4 is a configuration circuit diagram showing a non-inverting type track/hold circuit according to a second embodiment of the present invention. 1st
The same parts as in the figure are given the same symbols. 10 has two input stages 101 and 102 and an output stage connected to their outputs, and selects one of the input stages 101 and 102 by switching the operating current supplied to the input stages 101 and 102. ”/H amplifier, an input signal V1o is applied to the non-inverting input terminal of the first input stage 101,
The inverting input terminal is connected to the output terminal of output stage 103. Here, the input stage is 1ot, and the first stage of 102 is F B 'T'
It consists of a differential circuit. Hold capacitor CH
is connected between the inverting input terminal of the second manual power stage 102 and the output terminal of the output stage 103 of the /H amplifier 10, and the tank pink resistor R3 is connected between the hold capacitor CH and the output stage 10
3, and the FET switch SW2 is inserted between the input stage 10
It is connected between the inverting input terminal of No. 2 and the common, and its on/off is controlled in conjunction with the switching of the operating current. SW6
is a FET connected between the non-inverting input terminal of the input stage 102 and the common, and whose on/off is controlled in conjunction with SW2.
The switch C2 is a capacitor with the same capacity as the hold capacitor CH connected in parallel with the FET switch SW6, and is used to compensate for the pedestal voltage generated when the FET switch SW2 switches. 11 has one end connected to a negative voltage source 3- A constant current source 2 connects to the input stage 101 or 102 of the T/H amplifier 10 to supply an operating current to the input stage 101 or 102;
This is a current switch that can be connected to either the H side).

As in the case of Fig. 1, the bootstrap circuit is F E
'! 'Level shift the drain voltage of switch SW5 by 1
- After level shifting by 5V (for TTL level) in circuit 5, the output is supplied to the power supply of flip-flop 6, and the flip-flop circuit 6 is driven in synchronization with the T/H clock or S-lock, and the flip-flop The output of circuit 6 causes switch SW2. It drives SW6.

Next, its operation will be explained.

(a) Track mode In the track mode, in FIG. 1, FBT switch SW2. SW6 is turned on, and current switch 2 is connected to the 1' side. Input signal Vin is input stage 101 and output stage 1
It passes through a track amplifier with a gain of 1 in combination with 03, and a T/H output n output equal to the input signal 2 appears at 4. At this time, a current I that charges the hold capacitor CH flows through the FET switch SW2, and the F
The drain voltage of the ET switch SW2 fluctuates due to a voltage drop due to its on-resistance (several 100 Ω). C and C, SW2
and SW5 are elements with the same characteristics, respectively, so the drain voltage of FET switch SW5 changes exactly the same as the train voltage of SW2. As a result, as in the case of Fig. 1, the gate-drain voltage ■
gd becomes constant (here, 5V).

(b) During hold mode In hold mode, switch SW2 is set at the same timing.
．． SW6 turns off and current switch 2 falls to the H side. When the switch SW2 is turned off, the voltage value of the AC signal (input signal) at that time is held in the hold capacitor CI.

In other words, as mentioned in <a), since the voltage between the gate and drain of SW2 is constant, the capacitance Cgd between the gate and drain of SW2 is constant, and the change in the hold timing caused by the change in the switching time constant is eliminated, and the waveform Distortion can be reduced.

FIG. 5 is a diagram showing the frequency characteristics of the effective number of bits obtained through experiments for the track/hold circuit described above, and shows that the accuracy is improved over the entire frequency band compared to the conventional example.

FIG. 6 shows the frequency characteristics of second harmonic distortion obtained through experiments for the track/hold circuit described above. It can be seen that harmonic distortion has been significantly improved in the high range.

In the non-inverting track/hold circuit shown in FIG. 4, the output of the level shift circuit 5 may be connected to the power supply of the differential switch 7 as in the case shown in FIG.

Furthermore, in the non-inverting track/hold circuit of FIG. 4, the voltage at the drain terminal of SW2 may be directly fed back to the bootstrap circuit via an amplifier with high input impedance, as in the case of FIG. 3.

Furthermore, since the track/hold circuits of each of the above embodiments are used in common at least at their output stage, the AC amplitude applied to the FET switch SW2 is relatively small, and this can be further reduced by the bootstrap circuit, so that high-resolution AD It is particularly effective when used in converters. Also, the configuration becomes easier.

<Effects of the Invention> As is clear from the explanation below, according to the present invention,
By canceling the voltage drop caused by the switch-on resistance with a bootstrap circuit, a track/hold circuit in which the timing of data acquisition is constant without being modulated can be realized with a simple configuration.

[Brief explanation of drawings]

FIG. 1 shows the first rack/thread loop circuit according to the present invention
FIG. 2 is a configuration circuit diagram showing a first modification of the track/hold circuit according to the present invention;
FIG. 3 is a configuration circuit diagram showing a second modification of the track/hold circuit according to the present invention, FIG. 4 is a configuration circuit diagram showing a second embodiment of the track/hold circuit according to the present invention, and FIG. 6 and 6 are characteristic curve diagrams of the track/hold circuit shown in FIG. 4, FIG. 7 is a configuration circuit diagram showing a conventional track/hold circuit, and FIG. 8 is for explaining the operation of the device shown in FIG. 7. This is a diagram. 1.10... Track/hold amplifier, 4... Output terminal, 5... Level shift circuit, 6... D flip-flop, 7... Differential switch, 103... Output stage, CH ...Hold capacitor, SW2...F
E 'r'Sui Figure 1 Figure 2 Ze55 Illustrated 7) I'H1'JlIR (/4z) ldoπK lρθ change to χ n cycle yL number (Hz> Funeral diagram T/) - I T /H

Claims (1)

[Scope of Claims] A track/hold amplifier that performs track operation and hold operation with at least an output stage in common; one end of the track/hold amplifier is connected to the output terminal of the track/hold amplifier; A hold capacitor connected to the inverting input terminal of the track/hold amplifier, an FET switch connected between the other end of this hold capacitor and a common, and a level shift circuit that inputs a voltage corresponding to the voltage at the other end of the hold capacitor. and the voltage corresponding to the output of this level shift circuit.
A track/hold circuit comprising a drive circuit that turns on a T switch.