JPS587190A - Envelope generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope generation circuit that applies an envelope (=j) to a scale signal having a frequency corresponding to each scale a.

The conventional envelope generating circuit is a Kunister (P-channel MO8) whose source electrode is connected to the power supply voltage 7 and whose on/off control is controlled by the envelope instruction signal t/(cTha, rgθ) as shown in FIG. 1) (hereinafter referred to as PMO8), a charging/discharging circuit consisting of a capacitor (2) and a resistor (3) connected to PMO8, for output level control and whose resistance value is the same as the resistor (
Much larger voltage dividing resistor (4) than 3), puosm
an analog switch (5) inserted between the first connection point of the capacitor (21) and the voltage dividing resistor (4) and controlled on/off by the scale signal φ, a coupling capacitor (6), an input protection resistor (7), It consists of an amplifier circuit consisting of an inverter (8) and a resistor (9), and an output terminal (10).
A transistor (13) is connected to drive the speaker (21) via a low resistance transistor (21).
The pin (16) is a terminal for connecting external components such as capacitors and resistors.

In addition, in such conventional circuits, the voltage dividing resistor (4), which has a large number of capacitors and resistors, is replaced by the charge/discharge resistor (3).
Capacitor (2) and resistor (
3) The time constant to be determined by the voltage dividing resistor (4) is affected by the voltage dividing resistor (4).As the impedance conversion mechanism includes an amplifier circuit consisting of an inverter (8) and a resistor (9), there is a risk of oscillation. There were other drawbacks as well, such as current constantly flowing through the amplifier circuit.

The present invention aims to provide a novel envelope generation circuit that eliminates these drawbacks at once.

Embodiments of the present invention will be described below with reference to the drawings.

Figure 2 is a circuit diagram of an embodiment of the present invention.
and the drain electrode is connected to the terminal 118)l:″-,
Envelope instruction signals ch, a, r gθ indicating the timing to attach the envelope are applied to the gate-i pole. PMO8, Lll are terminals (capacitor connected to the country, (20) is the output terminal 1z1) A resistor connected to, (
Two are E-channel MOS transistors (hereinafter referred to as %NMOS), which are connected to the drain electrode and the gate electrode, and the source terminal is connected to the terminal 1), C23). is the gate electrode and drain electrode of N kl OS +221 (NMOS with the gate electrode connected and the source electrode connected to the output terminal 3, C1
One is that the source electrode is connected to the power supply voltage '174+i l2, the drain electrode is connected to the drain electrode of NMO8 (2), and the scale signal O having a frequency corresponding to each scale is applied to the gate electrode. ,(,Sifi
) is NMO8 whose drain magnetic pole is connected to the source magnetic pole of NMOS +23), that is, the output terminal t24), and whose source magnetic pole is applied to the gate electrode;
(1) is a transistor + for driving a speaker (28) via a resistor (27) as in the conventional example shown in Fig. 1.
291 are PHM'd. Note that in NMO8+221 and (2), the substrate is connected to the source electrode in order to prevent the influence of bag gate bias.

Next, the operation of this embodiment will be explained with reference to FIG.

Figures 6a) to 6) show waveforms at various parts of the embodiment shown in Figure 2.
When e goes to “L” level, P M OS C17)
is turned on, so capacitor 4 is charged to the can source voltage yaa. Then, when the signal oharge reaches the rHJ level, P M OS +17) is turned off, so the '4 load stored in the capacitor (19) becomes N M OS
+22) and the resistor (20), and the terminal (I
The 4th place of 81 is NMO8+2:i from the ground potential VSS
The voltage decreases according to the discharge curve toward yt, which is a potential higher by the threshold voltage of 5. Signal oha again
When rgθ reaches the rLJ level, the condenser ffl is charged and the same goes for the following (=envelope instruction signal a h a,
Charging and discharging are repeated according to rg. NMO8f
Since the gate potential of "2" is the same potential as the '1 position of terminal 0, a voltage Va having a charge/discharge curve as shown in *5 ZI port is applied to the gate electrode of NMo5c! This charge/discharge curve is the envelope tonal.

By the way, p y o s + 25) and N M OS
A scale signal φ is applied to the gate electrode of (26), and when the scale signal φ is l”HJ (7), the PMO19f2
■ is off and NMO5 (26) is on, so NMO8+
23) source electrode or output terminal (24J is the ground point VSS. When the scale signal i is rLJ, N
M OS (26) is off L I-' M OS+25
Since 1 is turned on, the power supply voltage ■dd is N M OS 12
3) is supplied to the drain's awakening electrode. Since NMO8 is the source magnetic pole, the voltage obtained by subtracting the threshold voltage Vt from the gate potential VO is the source electrode, that is, the output terminal (2
4) Hail to you. Therefore, as shown in Fig. 6, the output signal V011t has the same frequency as the frequency signal f, the highest level is cld-t, and the lowest level is VS.
A signal having a charging/discharging curve S is output. That is, the scale signal with the envelope is outputted from the output terminal C2 as the output signal yout. This signal yout drives the transistor C through the resistor +27, so that a single-level signal with an envelope is generated from the speakers (2~).

Here, if the resistor (27) is a variable resistor, the volume of the sound generated from the speaker (2) can be adjusted by this variable resistor. Also, instead of using the speaker as an electroacoustic transducer, , when using a high impedance element such as a piezoelectric buzzer, a transistor (2!
++ becomes unnecessary.

Next, an application example of the present invention is shown in FIG.

In the circuit shown in Figure 4, the terminal (
An analog switch t'io) is inserted between the source electrode of nuost2Z and the source electrode of nuost2Z.
The configuration is exactly the same as that of the previous embodiment. This analog switch +:10) is controlled to be turned on/off by the signal duty.
In this embodiment, instead of connecting the capacitor f (2) and the resistor (3) to the same terminal (14I) as in the conventional example shown in FIG. Connect the capacitor (19) and resistor (2) to the terminal U barrel, t21).
(1) Since the configuration is such that the two are connected to each other, this type of control is possible.

As mentioned above, the envelope generating circuit according to the present invention not only determines the time constant, that is, the envelope more reliably than the capacitor and resistor (2), but also requires fewer capacitors and resistors, and has fewer terminals than conventional circuits. In addition, as the impedance conversion mechanism uses a source follower MOS (MOS) transistor instead of an amplifier circuit consisting of an inverter and a resistor, there is no risk of oscillation, and it is possible to prevent unnecessary current from flowing at times other than when producing sound. .

Furthermore, since the configuration can be configured without using any analog switches, the number of elements can be extremely reduced, and external components such as capacitors and resistors can be connected to separate terminals. It is possible to insert an analog switch without having to do so, and this also makes it possible to control the time constant.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional example of an envelope generation circuit.
FIG. 2 is a circuit diagram showing an embodiment of the envelope generating circuit according to the present invention, FIG. FIG. Explanation of main number 4 ('3■...Analog switch, (8)...Inverter, l:Ml...Transistor, (lJf281-
x Beaker, C)2rllHa-NtYannelM
O8) Kunjistha. Applicant: Sanyo Shiki Co., Ltd. and one other person

Claims (1)

[Scope of Claims] 1) One end is connected to a first potential (a first switching means connected to the other and controlled on/off by an envelope instruction signal; and a first switching means connected between the first switching means and the second potential); a connecting point between the capacitor and the first switching means (=a first 5-MOS transistor to which a drain electrode and a gate electrode are connected);
O+3) A gate pole is connected to a resistor connected between the source electrode of the Kunster and the second potential, and a connection point between the capacitor and the first switching means, and the source electrode is an output terminal. a second MOS transistor connected to the second MOS transistor, one end of which is connected to the second MOS transistor, and the other end of which is connected to the first or second potential, and which are turned on and off at different timings according to a scale signal. 1. An envelope generating circuit comprising second and sixth switching means controlled in such a manner that an envelope is attached to the scale number 1 in response to the envelope instruction signal. 2. In claim 1, the first switching means is constituted by a t5B MOS transistor to which an envelope signal is applied to the gate electrode, and the second and sixth switching means are constituted by different channels.・4th and 50th:+
An envelope generating circuit characterized in that it is constructed from a Mo5l-Fungister.