JPS6213114Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope generation circuit that adds an envelope to a scale signal having a frequency corresponding to each scale.

As shown in FIG. 1, the conventional envelope generation circuit includes a P channel MOS transistor 1 (hereinafter referred to as PMOS) whose source electrode is connected to a power supply voltage Vdd and whose on/off control is controlled by an envelope instruction signal charge. , a charging/discharging circuit consisting of a capacitor 2 and a resistor 3 connected to the PMOS, a voltage dividing resistor 4 for output level control whose resistance value is much larger than that of the resistor 3, and a PMOS
an analog switch 5 which is inserted between the connection point of the capacitor 1 and the capacitor 2 and the voltage dividing resistor 4 and is controlled on and off by the scale signal φ; a coupling capacitor 6;
It is composed of an input protection resistor 7, an amplifier circuit consisting of an inverter 8 and a resistor 9, and a transistor 13 for driving a speaker 12 is connected to an output terminal 10 via a resistor 11. Also, 1
4, 15, and 16 are terminals for connecting external components such as capacitors and resistors.

In such a conventional circuit, even if the number of capacitors and resistors is large, and the voltage dividing resistor 4 is much larger than the charging/discharging resistor 3, the capacitor 2
The time constant to be determined by and resistor 3 is voltage dividing resistor 4
Since it has an amplification circuit consisting of an inverter 8 and a resistor 9 as an impedance conversion mechanism, there is a risk of oscillation, and current always flows through the amplification circuit even when not producing sound.

The present invention aims to provide a novel envelope generation circuit that eliminates these drawbacks at once.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention,
17 is an envelope instruction signal whose source electrode is connected to the power supply voltage Vdd and whose drain electrode is connected to the terminal 18, indicating the timing to apply the envelope.
PMOS where charge is applied to the gate electrode, 19 is a capacitor connected to terminal 18, 20 is terminal 2
1, a resistor 22, an N-channel MOS transistor (hereinafter referred to as NMOS) whose drain electrode and gate electrode are connected to the terminal 18, and whose source electrode is connected to the terminal 21, and 23, whose on/off is controlled by a scale signal φ. analog switch, 2
4 is an NMOS whose gate electrode is connected to the gate electrode and drain electrode of the NMOS 22 via the analog switch 23, whose source electrode is connected to the output terminal 25, and whose drain electrode is connected to the power supply voltage Vdd;
6 and 27 have their drain electrodes connected to the gate electrode and source electrode of the NMOS 24, respectively, the source electrodes are both connected to the ground potential Vss, and the scale signal φ is applied to the gate electrodes via the inverter 28.
This is an NMOS, and a transistor 31 for driving a speaker 30 is connected to the output terminal 25 via a resistor 29, similar to the conventional example shown in FIG.
In the NMOS 22 and 24, the substrate is connected to the source electrode in order to prevent the influence of back gate bias.

Next, the operation of this embodiment will be explained with reference to FIG.

3A to 3D show the waveforms of each part of the embodiment shown in FIG. 2, and the envelope instruction signal
When the charge becomes "L" level, the PMOS 17 is turned on and the capacitor 19 is charged to the power supply voltage Vdd. When the signal charge becomes "H" level, the PMOS 17 is turned off, so the charge stored in the capacitor 19 is transferred to the NMOS 22 and the resistor 20.
is discharged through the terminal 18, and the potential of the terminal 18 is ground potential.
It decreases according to the discharge curve toward Vt, which is a potential higher than Vss by the threshold voltage of the NMOS 22. When the signal charge goes to the "L" level again, the capacitor 19 is charged, and charging and discharging are repeated in the same manner in accordance with the envelope instruction signal charge. The gate potential of NMOS22 is the same as the potential of terminal 18, therefore, NMOS22
A voltage V _G having a charging/discharging curve as shown in FIG. 3(b) appears at the gate electrode, and this charging/discharging curve becomes an envelope.

By the way, analog switch 23 and NMOS 2
The scale signal φ or its inverted signal is applied to 6 and 27, and when the scale signal φ becomes “H”,
NMOS26 and 27 are turned off and analog switch 2 is turned off.
3 turns on. Therefore, a voltage obtained by subtracting the threshold voltage Vt from the gate potential V _G appears at the source electrode of the NMOS 24 . On the other hand, when the scale signal φ becomes "L", the analog switch 23 is turned off.
Since NMOS26 and 27 are turned on, NMOS24
The potential of the gate electrode and source electrode of is the ground potential.
Becomes Vss. Therefore, as shown in FIG. 3D, the output signal Vout is a signal having the same frequency as the scale signal φ and having a charge/discharge curve with the highest potential being Vdd-Vt and the lowest potential being Vss. The Rukoto. That is, the scale signal with the envelope is output from the output terminal 25 as the output signal Vout. This signal Vout drives the transistor 31 via the resistor 29, so that a scale signal with an envelope is produced from the speaker 30.

Note that if the resistor 29 is a variable resistor, the volume of the sound generated from the speaker 30 can be adjusted by this variable resistor. Furthermore, if a high impedance element such as a piezoelectric buzzer is used instead of a speaker as the electroacoustic transducer, the transistor 31 is not necessary.

As described above, the envelope generating circuit according to the present invention not only reliably determines the time constant, that is, the envelope, using the capacitor and resistor, but also requires fewer capacitors and resistors, and has fewer terminals than conventional circuits. In addition, as the impedance conversion mechanism uses a so-called source follower MOS transistor with a gain of 1, instead of using an amplifier circuit consisting of an inverter and a resistor, there is no risk of oscillation, and furthermore, unnecessary current does not flow when the sound is being produced. can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional example of an envelope generating circuit, Fig. 2 is a circuit diagram showing an embodiment of an envelope generating circuit according to the present invention, and Figs.
FIG. 3 is a waveform diagram showing waveforms of various parts of the example shown in the figure. Explanation of main drawing numbers, 1, 17...P channel
MOS transistor, 2,19...capacitor,
3,20...Resistor, 4...Voltage dividing resistor, 5,23...
...analog switch, 8,28...inverter,
13, 31...transistor, 12,30...speaker, 22, 24, 26, 27...N channel MOS transistor.

Claims (1)

[Claims for Utility Model Registration] 1. A first switching means having one end connected to a first potential and controlled on/off by an envelope instruction signal, and a first switching means connected between the first switching means and a second potential. a first MOS transistor having a drain electrode and a gate electrode connected to a connection point between the capacitor and the first switching means;
A gate electrode is connected to a connection point between the capacitor and the first switching means via a resistor connected between the source electrode of the transistor and the second potential, and an analog switch that is on/off controlled by a scale signal. and a second MOS transistor whose source electrode is connected to the output terminal; one end connected to the second potential, and the other end connected to the gate electrode or the source electrode of the second MOS transistor; A second switch is controlled to turn on and off at a timing different from that of the analog switch based on a musical scale signal.
and third switching means, wherein an envelope is attached to the scale signal in response to the envelope instruction signal. 2. In claim 1 of the claims for registration of a utility model, the first switching means is constituted by a third MOS transistor to which an envelope instruction signal is applied to the gate electrode, and the second and third switching means are configured by applying a scale instruction signal to the gate electrode. An envelope generating circuit comprising fourth and fifth MOS transistors to which an inverted signal is applied.