JPS587194U - Envelope generation circuit - Google Patents
Envelope generation circuitInfo
- Publication number
- JPS587194U JPS587194U JP10098981U JP10098981U JPS587194U JP S587194 U JPS587194 U JP S587194U JP 10098981 U JP10098981 U JP 10098981U JP 10098981 U JP10098981 U JP 10098981U JP S587194 U JPS587194 U JP S587194U
- Authority
- JP
- Japan
- Prior art keywords
- switching means
- envelope
- whose
- potential
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はエンベロープ発生回路の従来例を示す回路図ζ
第２図は本考案によるエンベロープ発生回路の実施例を
示す回路図、第３図イル二は第２ −図に示す実施例
の各部の波形を示す波形図である。
主な図番の説明、１．１７・・・ＰチャンネルＭＯＳト
ランジスタ、２．１９・・・コンデンサ、３゜２０・・
・抵抗、４・・・分圧抵抗、５．２３・・・アナログス
イッチ、８．２８・・・インバータ、１３．３１・・・
＼トランジスタ、１２．３０・・・スピーカー
、２２゜２４．２６．２７・・・ＮチャンネルＭＯＳ）
ランジスタ。 −Figure 1 is a circuit diagram ζ showing a conventional example of an envelope generation circuit.
FIG. 2 is a circuit diagram showing an embodiment of the envelope generating circuit according to the present invention, and FIG. 3 is a waveform diagram showing waveforms at various parts of the embodiment shown in FIGS. Explanation of main figure numbers, 1.17...P channel MOS transistor, 2.19...Capacitor, 3゜20...
・Resistance, 4... Voltage dividing resistor, 5.23... Analog switch, 8.28... Inverter, 13.31...
＼Transistor, 12.30...Speaker, 22゜24.26.27...N channel MOS)
Ranjista. −
Claims (2)
号によりオンオフ制御される第１のスイッチング手段と
、該第１のスイッチング手段と第２の電位との間に接続
されたコンデンサと、該コンデンサと前記第１のスイッ
チング手段の接続点にドーレイン電極及びゲート電極が
接続された第１のＭＯＳトランジスタと、該第１のＭＯ
Ｓトランジスタのソース電極と前記第２の電位との間に
接続された抵抗と、音階信号によりオンオフ制御される
アナ、ログスイッチを介して前記コンデンサと第１のス
イッチング手段との接続点にゲート電極が接続され且つ
ソー不電極が出力端子に接続された第２のＭＯＳ）ラン
ジスタと、一端が前記第２の電位に各々接続されると共
に他端が前記第２のＭＯＳトランジスタのゲート電極又
ぽソース電極に接続され且つ前記音階信号により前記ア
ナログスイッチとは異なるタイミングでオンオフするよ
う制御される第２及び第３のスイッチング手段とより成
り、前記エンベロープ指示信号に応じて前記音階信号に
エンベロープを付けるよう−にしたことを特徴トするエ
ンベロープ発生回路。(1) a first switching means whose one end is connected to a first potential and whose on/off control is controlled by an envelope instruction signal; a capacitor connected between the first switching means and the second potential; and the capacitor. and a first MOS transistor having a drain electrode and a gate electrode connected to the connection point of the first switching means;
A gate electrode is connected to the connection point between the capacitor and the first switching means via a resistor connected between the source electrode of the S transistor and the second potential, and an analog/log switch controlled on/off by a scale signal. a second MOS transistor whose one end is connected to the second potential and whose source electrode is connected to the output terminal, and whose other end is connected to the gate electrode or source of the second MOS transistor. second and third switching means connected to the electrodes and controlled by the scale signal to turn on and off at different timings from the analog switch, and configured to apply an envelope to the scale signal in accordance with the envelope instruction signal. An envelope generating circuit characterized in that it is set to -.
１のスイッチング手段をゲート電極にエンベロープ指示
信号が印加ぎれる第３のＭＯＳ ）ランジスタより構成
し、第２及び第３のスイッチング手段をゲー、ト電極に
音階信号の反転信号が印加される第４及び第５のＭＯＳ
）ランジスタより構成したことを特徴とするエンベロ
ープ発生回路。(2) Utility model registration In claim 1, the first switching means is constituted by a third MOS transistor to which an envelope instruction signal is applied to the gate electrode; fourth and fifth MOSs to which an inverted signal of the scale signal is applied to the second electrode;
) An envelope generating circuit characterized in that it is composed of transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10098981U JPS587194U (en) | 1981-07-06 | 1981-07-06 | Envelope generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10098981U JPS587194U (en) | 1981-07-06 | 1981-07-06 | Envelope generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS587194U true JPS587194U (en) | 1983-01-18 |
| JPS6213114Y2 JPS6213114Y2 (en) | 1987-04-04 |
Family
ID=29895661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10098981U Granted JPS587194U (en) | 1981-07-06 | 1981-07-06 | Envelope generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS587194U (en) |
-
1981
- 1981-07-06 JP JP10098981U patent/JPS587194U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6213114Y2 (en) | 1987-04-04 |
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