JPH05503621A - CMOS level shifter circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] CMOS level shifter circuit This invention is made under Contract No. 33615-88-C-1825 awarded by the Department of the Air Force. This was done with the support of the government. The Government has certain rights in this invention.

m minutes summer - The present invention relates to logic circuits, and more particularly to complementary metal oxide semiconductor (CMO) circuits. S) Regarding the level shifter circuit configuration.

Background of the invention Many logic, memory and timing configurations require different drive voltages Communication between functional blocks is necessary. The voltage level shifter is one The voltage level available at the output of the block is the voltage level of the interconnected blocks. Provide interfaces where bell requirements are not met.

U.S. Pat. No. 4,618.785 (H. van Tran) describes an n-channel ・Open CMO5 differential sense amplifier including level shifter and differential sense amplifier. It shows. This level shifter uses only n-channel transistors. This cell loses its threshold voltage when supplying the output image (rlJ) signal. The amplifier uses complementary fiMO5) transistors, and the level shift It can perform its functions. It is the output coupled to the input of the differential sense amplifier. output voltage level lower than the same low voltage level associated with a level shifter with cannot be supplied.

Voltage level sick designs are well known in the art, but are often , there are special operating conditions and device characteristics that result in poor operation of known circuits, e.g. , flat panel displays (F!4, liquid crystal displays) are very Because of the discharge of transistors with large time constants, special interfaces are often required. 0 circuits that require a chair circuit can be formed on top of a glass panel using thin film technology. If the characteristics of this thin film device (e.g. field effect transistor) are In such devices, proper operation cannot be determined as precisely as in other devices. must be ensured over a wide range of conditions and equipment parameters.

Adapted to work with widely varying device characteristics, Voltage levels suitable for implantation using CMO3I film transistors on glass ・A shifter circuit is required.

^Insa 1st person Viewed from one aspect, the invention provides first and second p-channel field effect transistors. a third and fourth n-channel field effect transistor, and an inverting means. It is aimed at voltage level shifting circuit configurations that include. each of the transistors each have a gate and a first output. The inverting means has this circuit configuration. an input coupled to an input terminal and a gate of the first transistor; and an output coupled to the gate of the gate. The output terminal of the circuit configuration is the second and and the first output of the fourth transistor. 1st and 3rd tran The first output of the transistor is coupled to the gates of the third and fourth transistors. Ru.

In a typical implementation, the second output of the first and second transistors has a positive of the third and fourth transistors is coupled to a voltage m (e.g. -t-isv) The zero inverting means, the second output of which is coupled to a negative voltage a (e.g. -5■), An inverter with a supply voltage terminal coupled between +15V and Ov. child The human power signal voltage level applied to the input terminal of the circuit configuration is +15V and +15V, respectively. Logic ``1'' (high) and ``0'' (low) voltage levels. This time The voltages developed at the output terminals of the circuit configuration are +15V and -5V logic "1" respectively. ” and “0” voltage level.

The level shift circuit configuration of the present invention is! ! Membrane technology is used to coat glass surfaces (e.g. liquid A metal oxide semiconductor (MOS) transistor formed on a crystal display) Even taking into account changes in the threshold voltage that exist, there is no acceptable range. It is capable of functioning fully within its surroundings.

Viewed from another aspect, the present invention includes a pair of voltage buses and a first and second conductive terminal. one MOS transistor and a third and fourth MOS transistor of opposite conductivity type. It is directed to level shifter circuits including transistors. Each transistor is The conductive MIS gate is made of Ami. The first and third transistors The transistors 2B and @4 are connected in series between the voltage buses. Connected to columns. A node between the first and second transistors is connected to the second and second transistors. and the gate of the fourth transistor. One of the first and second levels An input signal having an input signal is applied to the gate of the first transistor, and an input signal having A voltage is applied to the gate of the third transistor. 2nd and 4th tran The nodes between the transistors are connected to the second and fourth transistors in response to the first level input signal. is coupled to one of the voltage buses through one of the transistors to a second level input signal. to the other one of the voltage buses through the other one of the second and fourth transistors accordingly Connected.

The present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings and claims. It will be easy to understand.

Brief description of the drawing FIG. 1 is a schematic block diagram of one level shifter circuit according to the prior art.

FIG. 2 is a schematic block diagram of another level shifter circuit according to the prior art.

FIG. 3 is a schematic block diagram of a level shifter circuit according to one embodiment of the present invention. 4 is a schematic block diagram of a level shifter circuit according to another embodiment of the present invention.

wasted member μ base plate Referring to FIG. 1, one level shifter circuit 10 according to the prior art is shown. Ru. The level shifter circuit 10 includes an input terminal (vrN) 26, a supply voltage terminal 32 . 34 and 36, output terminal (VOUT) 42, inverter 12.14 and 16 , p-channel MOS transistors 18 and 20, and n-channel M It includes OS transistors 22 and 24. The input terminal 26 is an inverter 12. The output of inverter 12 is inducted via node 28. Connected to the power of the converter 14 and the gate of the p-channel MO5) transistor 18 has been done. The output of inverter 14 is connected via node 30 to a p-channel MOS Connected to the gate of transistor 20. p-channel MO3) Rungis the sources of inverters 18 and 20, and the first supplies of inverters 12.14 and 16. The supply voltage terminal is connected to a positive voltage source +Vdd at supply voltage terminal 32.

the drains of transistors 22 and 24 and the second supply voltage of inverter 16; The voltage terminal is connected to the negative voltage H-Vss2 and to the supply voltage terminal 34. stomach The second supply terminals of inverters 12 and 14 are connected to the reference voltage fiVssl and the supply It is coupled to voltage terminal 36. The drain of transistor 18 is connected via node 38. connected to the drain of transistor 22 and the gate of transistor 24. Ru. The drain of transistor 20 is connected to the drain of transistor 24 through node 40. and the input of the inverter 16. The output of the inverter 16 is It is connected to the output terminal (VOUT) 42.

Typically has logic 0 (low, "0") and logic 1 (high, "1") states A binary signal is applied to VIN (terminal 26). Positive supply voltage at terminal 32 +Vdd is, for example, +15V. Negative supply voltage at i1 child 34 -Vss 2 is, for example, -5■. The reference supply voltage Vssl at terminal 36 is, for example It is OV (earth). The input signal applied to terminal 26 is +15V high (“1 ) level and a low (job) level of OV (earth). Therefore, terminal 2 The input signals applied to 6 have logic levels of OV and +15V. The technique As is well known in the art, an inverter has a logic zero in response to a logic zero at its input. Logic 1 is used to generate logic 0 in response to logic 1 by human power. inverter 12 and 14 are connected between +15V and Vssl, for example OV (ground). It is continued. Therefore, "0" from inverters 12 and 14 is at Ov level , and the "1" from inverters 12 and 14 has a +15V level.

Inverter 16 is connected between supply voltages +Vdd and -Vss2. stomach rQJ from inverter 16 has a -Vss2 voltage level, and rl from it is +Vdd' voltage level.

When the voltage level applied to the terminal 26 is 0■ and the input rQJ level, the inverter Node 28 at the output of The input of the controller 14 and the gate of the transistor 18 are at the +15V “1” level. be. Inverter 14 produces a ``0'' at node 30, which The current flowing through transistor 20 that enables (biases on) 4. Pulling up the voltage at node 40 towards +Vdd. Tran Register 18 is disabled by a "1" level at its gate (node 28). (bias off, turn off) and becomes non-conductive. The node 40 is When charged to +V, dd, transistor 22 is enabled and node 3 8 to -Vss2. This disables transistor 24 , which then allows the voltage at node 40 to continue rising to +Vdd voltage level. At this time, the voltage at node 40 is ``rl'' (+15V ), so the output voltage of this circuit 10 at terminal 42 is ro'' (-5V -Vss2).

When input ``1'' is applied to terminal 26, node 28 is rO'' and transistor 18 is enabled and becomes conductive. The output of inverter 14, node 30 and The voltage at the gate of transistor 20 is "1", which means that transistor 20 Disable (turn off, bias off). Transistor 18 conducts When passed, it charges node 38 to +Vdd and +Vdd begins to conduct. enable transistor 24. Conduction through transistor 24 is Pulling (discharging) node 40 to -Vss2 in voltage, A voltage of -Vss2 disables transistor 22. This is Transistor 18, which is turned off, continues to charge node 38 to +Vdd. , which keeps transistor 24 enabled. on node 40 The obtained voltage of -Vss2 is inverted by the inverter 16 and output on the terminal 42. r1'' (+vad voltage).

The circuit of Figure 1 can provide the desired voltage as long as the transistor characteristics suitably match the circuit requirements. Provide pressure level. However, under some circumstances, relatively poor characteristics of the Level thick circuit 10 may not function because a resistor must be used. . For example, ms field effect transistors on glass substrates (e.g. liquid crystal displays) (e.g. MOS transistors) in optical displays and sensing devices. required. Such transistors have poor performance that can impair the operation of the circuit of Figure 1. exhibits new characteristics. The threshold voltage of p-channel transistor 18 is Level shift when significantly above the threshold voltage of channel transistor 22 Let us consider the operation of the terminal 10. If the input voltage applied to the input terminal 26 is When node 38 is -Vss2 and node 40 is +Vdd, from 0■ to +15V If the change occurs, transistor 20 will turn due to the high voltage level at node 30. It will be turned off. If the threshold of p-channel transistor 18 is significantly higher than the threshold of channel transistor 22, both are enabled. When conducting, the drain-source resistance of p-channel transistor 18 is significantly higher than the drain-source resistance of n-channel transistor 22. It can be. Therefore, p-channel transistor 18 causes the voltage at node 38 to , n-channel transistor 24 is enabled and turned on. It is not possible to raise (pull up) exactly as much as possible. This will book node 40. The output on terminal 42 is -Vss2 (5V) so that it remains qualitatively +15V. Therefore, when +Vdd is applied to the input, it will have an output voltage level of +Vdd. The output level of the circuit lO to be output may be -Vs　s　2, and therefore the output level of It will no longer function as a bell shifter.

Referring to FIG. 2, another prior art level shifter circuit 100 is shown.

Level shifter 100 consists of n-channel MO3) transistors 106, 108 . 110 and 112. Each transistor has a gate, drain and and source. The first input terminal VIN is the gate-off terminal of the transistor 106. and terminal 114. The second input terminal VIN" is a transistor 1° 8 and terminal 116. VIN’ is applied to VIN. Accepts logical inversion of the signal. The output terminal VOUT is the solenoid of transistor 108. the drain of transistor 112 and terminal 118 . first The power supply terminals are the drains of transistors 106 and 108, terminals 120 and and a power supply with a voltage +'Vdd. Transistor 110 and and 112 are both connected to terminal 122 and a power source having a voltage level -Vss2. Connected to the source. Input signal voltage of signals applied to VIN and VTN’ The voltage level is a “1” voltage level of +Vdd and a “0” voltage level of Vssl (not shown). voltage level, where Vssl is more positive than -Vss2 and more positive than +Vdd. Make it not exist. The source of transistor 106 and the drain of transistor 110 in is coupled to the gates of transistors 110 and 112 and to terminal 122. There is.

In one illustrative example of circuit 100, +Vdd-+15V, Vssl=OV( ground) and Vss2=-5V. applied to input terminals 114 and 116 The input signal that is input has a “1” logic level at +15V and a “0” logic level at have. "rl" applied to input terminal 114 enables transistor 106. (bias on) and transistor 106 and transistor 110 are turned on. A current path from +Vdd to -Vss2 is created. This is terminal 122 The voltage is raised to enable transistor 112, and transistor 112 is turned on. Attempt to conduct and lower the voltage of terminal 118 (VOIJT) to -Vss2. let At this time, the voltage at the terminal 116 is logic "0", OV. This is I , weakly enables transistor 108 because its gate is at a voltage This is because G1 can be negative by -Vss2. Like this transistor 10B attempts to pull the voltage at terminal 118 toward +Vdd. Therefore, the transistor Transistor 112 is strongly biased on and transistor 108 is weakly biased on. The voltage at output terminal 118 is -Vss2, logic output rO', typically Get closer to the target.

The input 'OJ (OV) applied to the input terminal (VTN) 114 is a transistor 106 is weakly biased on, and transistor 106 and transistor Establishing a current flow from +Vdd to -Vss2 through the terminal 110. this i ! , weakly biases transistor 112 on, which then turns on terminal 118. Attempt to pull the voltage down to -Vss2. At the same time, the transistor 108 It is strongly biased on by the input "1" applied to terminal 116. Therefore, A current path from +Vdd is created through transistors 108 and 112 .

Since transistor 108 is strongly biased on, there is no gain at output terminal 118. The voltage applied is +Vdd, which is not close to the logic output "1" <, the maximum level of the logic output "1" is +Vdd minus the threshold voltage of transistor 108, Therefore, the difference between the output voltage logic levels of circuit 100 is +Vdd and -Vss2. The difference between

Referring now to FIG. 3, a level knock circuit 200 according to the present invention is shown. Ru. Level shifter circuit 200 includes p-channel field effect transistor 206 and 20, n-channel field effect transistors 210 and 212, if and an inverter 202. Each of the transistors is typically an M.O. It is an S transistor and has a gate, a drain, and a source. Input terminal (VIN ) are the input of inverter 202, the gate of transistor 206 and terminal 214 is combined with The output terminal (VOUT) is the terminal of transistors 208 and 212. It is coupled to the drain and terminal 218. First power supply for inverter 202 The terminals are the sources of transistors 206 and 208, terminal 220 and +Vdd is coupled to a power supply having a voltage level of . The second voltage of inverter 202 The source supply terminal is connected to terminal 224 and a power supply having a voltage level of Vssl. It matches. The sources of transistors 210 and 212 are both connected to terminals 222 and 212. and -Vss2, where Vssl is more positive than +Vdd (more positive than -Vss2. The output of inverter 202 is , coupled to the gate of transistor 208 and terminal 216. transistor The drains of 206 and 210 connect to the gates of transistors 210 and 212. and terminal 204.

In the example of circuit 200, +Vdd=+15V, Vs s 1=OV ( ground) and Vss2 = 5V. The input signal applied to the VrN terminal is It has a "1" logic level of +15V and a "0" logic level of OV. input A logic “1” applied to terminal 214 disables transistor 206. (bias off). This causes transistor 210 to be disabled. , so that no current flows through it. This is transistor 212 Disable. The output of the inverter 202 (terminal 216) is At QJ(OV), this enables transistor 208. As such, the output The terminal (VOUT) 218 has a voltage level of 10 Vdd (+15 V), a logic output " It is drawn in a wide range up to 1. If applied to the input terminal (VIN) 214, If the input signal to be input is input rQJ (OV, Vs s 1), transistor 2 06 is enabled and transistor 208 is disabled. this is, Current path from +Vdd through transistor 206 and transistor 210 causes a voltage to rise at terminal 204, which enables transistor 212. and then make it conductive. Parasitic capacitance or load coupled to terminal 218 Enabled transistor 212 comes from a capacitor (both not shown). The initial current flow through is essentially between transistor 206 and transistor 21. It is the same as that flowing through 0. In this way, the output terminal (VOUT) 218 is A voltage level of -Vss2 (-5V) is applied through the enabled transistor 212. discharge in a wide range up to the logic output "0". Transistor 212 has a terminal When 218 reaches -VsS2, it stops conducting. Therefore, logic from 0 to +15V The input signals having a level are level-knotted in the circuit 200 and each -5v The output signal level becomes +15v. In this way, the output signal level is +Vd It has a potential difference equal to the gold cap between d and -Vss2.

Unlike the level sick circuit 10 of FIG. 1, the level shifter circuit 200 of FIG. Matching the threshold voltages of p-channel and n-channel transistors Therefore, the circuit operation of the level sick circuit 200 is regardless of differences in device thresholds that may occur when using transistors with different characteristics. I am in charge. Now referring to FIG. 4, the level sick times according to the present invention! 5400 is It is shown. The level thick circuit 400 includes a second human-powered inverter 404 and Essentially, except for the addition of the output sofa inverter 406 (shown inside the M-line rectangle) It is the same as the level sick circuit 200 of FIG. All of the inverter circuit 400 The parts and terminals that are the same as those of the level thick circuit 200 in FIG. , have the same reference numbers.

Buffer inverter 406 includes p-channel transistors 408 and An n-channel transistor 410 is included. Transistor 408 and and 4°10 are coupled to terminal 218. transistor 408 and The sources of 410 are coupled to power supply terminals 220 and 222, respectively.

The drains of transistors 408 and 410 are connected to the output of inverter circuit 400 ( VOUT). Buffer inverter 4 06 is used to provide increased current drive capability to the level thick circuit 400. It is used. It introduces an inversion resulting in the output signal developed at terminal 412. , the additional inversion provided by inverter 404 is provided by circuit 200 of FIG. required to generate essentially the same output signal waveform as that generated. in Inverter 404 has an input coupled to input terminal 402 of inverter circuit 400. , has an input coupled to inverter 202 and an output coupled to terminal 214 .

Each of inverters 404 and 202 is typically the same type as inverter 406. It includes a CMO5 inversion stage that performs.

The specific examples described herein are merely intended to illustrate the spirit and scope of the invention. You should understand that there are Improvements may be made consistent with the principles of the invention by those skilled in the art. It can be easily achieved by those who have attained it.

FIG.i ■　Kutti Chimi Ding FI6. 3 Summary book (translation) The level thick circuit includes a pair of voltage buses, a first and a second p-channel MO 3) transistor, and the third and fourth n-channel MO5) transistor Each transistor includes a gate that is conductive. The first one and a third transistor are connected in series between the pair of voltage buses, and the third transistor is connected in series between the pair of voltage buses. The second and fourth transistors of are in series between the pair of voltage buses! I[is , the node between the first and second transistors is It is connected to the gate of transistor No. 4.　First and second level 10 is applied to the gate of the first transistor so that the input signal has The inverse of the signal is applied to the gate of that second transistor. That voltage bus one of its second and fourth transistors in response to a first level input signal; connected through one side. The other side of that voltage bus is a second level input signal. is connected to the other of the second and fourth transistors, depending on the transistor.

Copy and translation of auxiliary equipment) submission form (Patent Law Article 184-8) July 23, 1992

Claims (12)

[Claims] 1. A voltage level shifting circuit configuration that includes the following requirements: first and second p-channel field effect transistors having first and second outputs; Ta; third and fourth n-channel channels, each having a gate and a first output; field effect transistor; a circuit configuration input terminal coupled to the gate of the first transistor; Circuit configuration output terminal coupled to the first output of the transistor; coupled to the circuit configuration input terminal and an output coupled to the gate of the second transistor. inverting means for inverting the signal applied to the force; and a first transistor thereof; The first output of the transistor is connected to the first output of the third transistor and the third and fourth transistors. It is connected to the gate of the transistor. 2. A voltage level switch whose inverting means is an inverter having an input and an output. Footing circuit configuration. 3. The voltage level shifting circuit configuration of claim 2, wherein: the inverter comprises: , a fifth p-channel field effect transistor and a sixth n-channel field effect transistor. an effect transistor, each of the fifth and sixth transistors having a gate and a first output; gates of its fifth and sixth transistors; the fifth and sixth transistors are coupled to the circuit configuration input terminal; A circuit configuration in which the first output of the star is coupled to the output of the inverter. 4. Further, a first power supply coupled to a second output of the first and second transistors. a second voltage coupled to the supply terminal and the second outputs of the third and fourth transistors; 4. The voltage level shifting circuit arrangement of claim 3, including a power supply terminal. 5. Further, the voltage level shifting circuit configuration of claim 4 including the following requirements: power supply terminal; and a fifth and a sixth transistor, each having a second output; A second output of the transistor is coupled to the first power supply terminal and is also coupled to the sixth transistor. A second output of the transistor is coupled to a third power supply terminal. 6. The first, second and third power supply terminals are connected to the first, second and third power supply terminals, respectively. 6. The voltage level shifter of claim 5 adapted to couple with a power supply source of claim 3. ing circuit configuration. 7. a third power source, the voltage of the first power source being more positive than the voltage of the second power source; 7. The voltage level shifting circuit arrangement of claim 6, wherein the voltage level shifting circuit arrangement is more positive than the voltage of the power supply. . 8. The voltage level shifting circuit configuration of claim 7 further comprising the following requirements: and a second inverter having an output, the input of which is connected to the input terminal of the circuit configuration. the output of which is coupled to the input of the first inverter, and whose output is coupled to the input of the first inverter; a first power supply terminal coupled to the supply terminal; and a third circuit configuration power supply terminal coupled to the power supply terminal. an inverter having a coupled second power supply terminal; and having an input and an output; a third inverter whose input is connected to the first output of the second and fourth transistors; the output of which is coupled to the output terminal of the circuit arrangement and the output of which is coupled to the output terminal of the circuit arrangement; a first power supply terminal coupled to a power supply terminal; a second circuit configuration power supply terminal; an inverter having a second power supply terminal coupled to the inverter; 9. Each of the second and third inverters is a p-channel field effect transistor. transistor and an n-channel field effect transistor, the p - the drains of the channel and n-channel transistors of the inverter output and the gates of its p-channel and n-channel transistors. 9. The voltage level shifter of claim 8, wherein the voltage level shifter is coupled to an input of the inverter. circuit configuration. 10. The voltage level of claim 9, wherein all transistors are MOS transistors. Shifting circuit configuration. 11. A level shifter circuit that includes the following requirements: a pair of voltage buses; first and second p-channel MOS transistors and third and fourth n-channel MOS transistors; - channel MOS transistor; Each transistor has a gate that controls conduction through it; and a third transistor connected in series between the pair of voltage buses; The second and fourth transistors are connected in series between the pair of voltage buses. ing; A node between the first and third transistors is a node between the third and fourth transistors. Connected to the gate of the register; An input signal having one of the first and second levels is applied to the first transistor. means for applying voltage to the gate; and means for applying an inverse of the input signal to the gate of the second transistor; and the fourth transistor in response to its first level input signal. , through one of its second and fourth transistors to one of the voltage buses; through the other of the second and fourth transistors in response to the input signal at the level of It is connected to the other side of the voltage bus. 12. During its operation, its first level input signal is essentially the first level of the voltage bus. The second level input signal is at the voltage applied to the voltage bus. 13. The level switch of claim 12 at a more positive voltage than the voltage applied to the second. Lid circuit.