CN100389449C - Source driver and its driving method - Google Patents
Source driver and its driving method Download PDFInfo
- Publication number
- CN100389449C CN100389449C CNB200510009400XA CN200510009400A CN100389449C CN 100389449 C CN100389449 C CN 100389449C CN B200510009400X A CNB200510009400X A CN B200510009400XA CN 200510009400 A CN200510009400 A CN 200510009400A CN 100389449 C CN100389449 C CN 100389449C
- Authority
- CN
- China
- Prior art keywords
- voltage
- circuit
- transistor
- source electrode
- quasi position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention relates to a source driver of a liquid crystal display device, which is used for driving at least one data line and comprises an input port for receiving a scheduled voltage level, an output port which is electrically connected to the data line and has an output voltage level, a voltage control circuit for controlling the output voltage level in a scheduled voltage range, a first differential amplifier for increasing the controlled output voltage level to the scheduled voltage level and a second differential amplifier for reducing the controlled output voltage level to the scheduled voltage level. The present invention also provides a source driving method of the liquid crystal display device.
Description
Technical field
The present invention relates to a kind of source electrode driver and driving method thereof, more especially about a kind of source electrode driver and driving method thereof of LCD.
Background technology
Fig. 1 is the driving circuit synoptic diagram of the LCD device 100 of a known active-matrix type.LCD device 100 has comprised a liquid crystal panel 110, which is provided with a thin film transistor (TFT) array 112, a gate driver circuit 120 and one source pole driving circuit 130.Thin film transistor (TFT) array 112 is made up of a plurality of thin film transistor (TFT) 113.The grid 113a of each thin film transistor (TFT) 113 is connected to a corresponding scanning line 114, and its source electrode 113b is connected to a corresponding data line 116, with and drain electrode 113c be connected to an end of the demonstration electric capacity 118 of a correspondence.Each shows that the other end of electric capacity 118 is connected to a common voltage VCOM.Gate driver circuit 120 is in order to provide switch-over control signal (sweep signal) to sweep trace 114, and source electrode drive circuit 130 is in order to provide level voltage to data line 116.
Fig. 2 is the part synoptic diagram of the source electrode drive circuit 130 of a typical liquid crystal.Source electrode drive circuit 130 comprises a voltage divider 200, a plurality of code translator 202 and a plurality of driver 204.Voltage divider 200 is formed by resistance (device) R1～Rn, in order to produce multi-level voltage.The multi-level voltage that voltage divider 200 produced is the selected input end 204a that exports driver 204 to via the switching of the switch 202a in the code translator 202.204 of each drivers are corresponding to each bar data line (as the data line 116 of Fig. 1) of liquid crystal panel, and connect individually via its output terminal 204b and drive each bar data line.
Fig. 3 is a United States Patent (USP) the 6th, 567, the circuit diagram of the driver 204 that is disclosed for 327 B2 numbers.This driver 204 has comprised on one and has drawn (pull high) differential amplifier 210, drop-down (pulllow) differential amplifier 212.Driver 204 has an input end 204a, in order to receiving a level voltage Vin, and has an output terminal 204b.The output voltage V out negative feedback of driver 204 is to the voltage input end Vin-of differential amplifier 210,212, and level voltage Vin inputs to voltage input end Vin+.
On draw differential amplifier 210 when having one between output voltage V out and voltage input end Vin+ voltage up during pressure reduction, on draw differential amplifier 210 just can move, use the voltage quasi position that output voltage V out up is increased to voltage input end Vin+.In addition, drop-down differential amplifier 212 is when existing one down during pressure reduction between output voltage V out and voltage input end Vin+ voltage, and drop-down differential amplifier 212 just can move, and uses the voltage quasi position that output voltage V out down is reduced to voltage input end Vin+.
The following general introduction of the manner of execution of driver 204.Output voltage V out can be a steady state (SS) when voltage input end Vin+ voltage equals Vin-voltage.When voltage is changed into Vin+ greater than Vin-, when promptly importing level voltage Vin greater than output voltage V out, only switch S 1 to S3 conducting (ON) makes transistor 220 be subjected to output voltage V 01 control and conducting, and output voltage V out begins to be increased to the voltage quasi position of Vin+ voltage then; At last, only switch S 0 conducting makes input end 204a and output terminal 204b short circuit, allows output voltage V out can be pulled to the voltage quasi position of input level voltage Vin more accurately.And when voltage is changed into Vin+ less than Vin-, when promptly importing level voltage voltage Vin less than output voltage V out, only switch S 4 to S6 conductings make transistor 222 be subjected to the control of output voltage V 02 and conducting, and output voltage V out begins to be reduced to the voltage quasi position of Vin+ voltage then; At last, only switch S 0 conducting makes input end 204a and output terminal 204b short circuit, allows output voltage V out can be pulled to the voltage quasi position of input level voltage Vin more accurately.
Yet, on draw for the differential amplifier 210, when output voltage V out levels off to VDD, and input level voltage Vin is during greater than Vout, on draw differential amplifier 210 just to be difficult to will Vout continue draw; And for drop-down differential amplifier 212, when output voltage V out levels off to VSS, and input level voltage Vin is during less than Vout, and drop-down differential amplifier 212 just is difficult to Vout is continued drop-down.Therefore, the output voltage V out scope of driver 204 is just restricted, and can't reach VSS～VDD four corner.
In view of this, the source electrode driver that the big LCD of a kind of driven scope need be provided is arranged just, to solve the existing problem of above-mentioned known technology.
Summary of the invention
One of the present invention purpose is to provide a kind of source electrode driver of LCD, and it can increase the driven scope, and can reduce the loss of electric weight.
Another purpose of the present invention is to provide a kind of source electrode driver of LCD, and it can dwindle the size of source electrode drive circuit, and can reduce the circuit manufacturing cost.
For reaching above-mentioned purpose, the invention provides a kind of source electrode driver, comprising:
One first differential circuit has an input end in order to receiving one first input signal, with an output terminal in order to according to this first input signal, produce one first output signal; And
One first voltage clamping circuit has the output terminal that an input end couples this first differential circuit, in order to strangulation first output signal between one first voltage quasi position and one second voltage quasi position;
Wherein, this first differential circuit is coupled to a high-potential voltage source, and the voltage quasi position in this high-potential voltage source is greater than this first voltage quasi position and this second voltage quasi position.
Above-mentioned source electrode driver is in order to drive at least one data line, and it comprises an input end, in order to receive the accurate position of a predetermined voltage; One output terminal is electrically connected to this data line and has the accurate position of an output voltage; One voltage clamping circuit is in order to be clamped to the accurate position of this output voltage in one predetermined voltage range; One first differential amplifier improves toward the accurate position of this predetermined voltage in order to will be somebody's turn to do by the accurate position of the output voltage of strangulation; And one second differential amplifier, low in order to will be somebody's turn to do toward the accurate potential drop of this predetermined voltage by the accurate position of the output voltage of strangulation.
According to source electrode driver of the present invention, it has comprised one first on-off circuit and a second switch circuit in addition, in order in the one scan line time, the accurate position of output voltage on the accurate position of a plurality of predetermined voltages and many data lines is switched to this first differential amplifier and this second differential amplifier in turn, be pulled to accurate of this a plurality of predetermined voltages individually with the accurate position of output voltage on will this many data lines by this first differential amplifier and this second differential amplifier.In view of the above, because many data lines can share this first and second differential amplifier, so the size of source electrode drive circuit can be reduced, and circuit manufacturing cost thereby be lowered.
The present invention provides a kind of driving method of source electrode driver in addition, comprises the following step:
First output signal of strangulation one first differential circuit output is between one first voltage quasi position and one second voltage quasi position; And
According to this first output signal and an input signal, produce one second output signal, and with this second output signal as this first output signal;
Wherein, this first differential circuit is coupled to a high-potential voltage source, and the voltage quasi position in this high-potential voltage source is greater than this first voltage quasi position and this second voltage quasi position.
This driving method is applied in the one source pole driver, in order to drive many data lines, each data line has the accurate position of an output voltage, wherein this source electrode driver comprises one first differential amplifier, in order to improve the accurate position of this output voltage, and one second differential amplifier, in order to reduce the accurate position of this output voltage, this method comprises the following step: the accurate position of the output voltage of each data line is clamped between one first voltage quasi position and one second voltage quasi position, make the accurate position of this output voltage greater than this first voltage quasi position, and less than this second voltage quasi position; And in a schedule time, receive the accurate position of output voltage and the accurate position of a corresponding predetermined voltage of each data line by this first differential amplifier and this second differential amplifier in turn, and the accurate position of the output voltage of each data line is pulled to the accurate position of this corresponding predetermined voltage individually.Comprise a following step in addition according to source driving method of the present invention: receive the accurate position of this corresponding predetermined voltage individually via each data line, make the accurate position of output voltage of each data line be equal to the accurate position of this corresponding predetermined voltage.
According to source driving method of the present invention, it can drive many data lines via two differential amplifiers, uses the use number that reduces differential amplifier, make that the size of source electrode drive circuit can be reduced, and the circuit manufacturing cost can be lowered.
Description of drawings
Fig. 1 is the driving circuit synoptic diagram of the LCD device of a known active-matrix type.
Fig. 2 is the part synoptic diagram of the source electrode drive circuit of a typical liquid crystal.
Fig. 3 is the circuit diagram of a known drive device.
Fig. 4 is the circuit block diagram of source electrode driver of the LCD of the embodiment of the invention.
Fig. 5 is the thin portion circuit diagram of source electrode driver of the LCD of Fig. 4 embodiment.
Fig. 6 A, Fig. 6 B and Fig. 6 C are urged to the accurate position of output voltage two specific embodiments of level voltage quasi position in the one scan line time in order to the source electrode driver of key diagram 5.
Fig. 7 is another alternate embodiment of the source electrode driver of Fig. 5.
Fig. 8 is another alternate embodiment of the source electrode driver of Fig. 7.
Symbol description among the figure:
The VCOM common voltage
R1, R2, R3, Rn resistance
Vin level voltage Vout output voltage
V01, V02, V03, V04 output voltage
VDD, VSS voltage source
Vin+ non-inverting input Vin-inverting input
S1, S2, S3, S4, S5, S6 switch
S7, S8, S9, S10, S11, S12 switch
CR1, CR2 constant current source
Vin1, Vin2 level voltage quasi position
Vout1, the accurate position of Vout2 output voltage VA, VB voltage quasi position
NH1, NH2, NH3, NH4, NH5, NH6, NH7 nmos pass transistor
PH1, PH2, PH3, PH4, PH5 PMOS transistor
PL1, PL2, PL3, PL4, PL5, PL6, PL7 PMOS transistor
NL1, NL2, NL3, NL4, NL5 nmos pass transistor
PC1, PC2, PC3 PMOS transistor
NC1, NC2, NC3 nmos pass transistor
VENA0, VENA1, VENB0, VENB1 control voltage
VPRE, VPREB, VTL, VTH control voltage
100 LCD device, 110 liquid crystal panels
112 thin film transistor (TFT) arrays, 113 thin film transistor (TFT)s
116 data lines 118 show electric capacity
120 gate driver circuits, 130 source electrode drive circuits
200 voltage dividers, 202 voltage dividers
202a switch 204 drivers
Draw differential amplifier 212 drop-down differential amplifiers on 210
220,228,230 PMOS transistors
222,224,226 nmos pass transistors
300 source electrode driver 300a, 300b input end
Draw differential amplifier on 300c, the 300d output terminal 302
302a non-inverting input 302b inverting input
304a non-inverting input 304b inverting input
308 first on-off circuits, 310 second switch circuit
312 the 3rd on-off circuits
Embodiment
Now please refer to Fig. 4, it shows the circuit block diagram of the source electrode driver 300 of LCD according to an embodiment of the invention.Source electrode driver 300 has two input end 300a, 300b, in order to receive level voltage quasi position Vin1, Vin2 individually by a voltage divider (voltage divider 200 as shown in Figure 2), and two output terminal 300c, 300d, in order to two data lines (data line 116 as shown in Figure 1) that are electrically connected to a liquid crystal panel individually, wherein have the accurate position of output voltage Vout1, Vout2 on two output terminal 300c, the 300d individually.Source electrode driver 300 comprises on one and draws (pull high) differential amplifier 302, drop-down (pull low) differential amplifier 304, a voltage clamping (clamp) circuit 306, one first on-off circuit 308, a second switch circuit 310 and one the 3rd on-off circuit 312.First on-off circuit 308 has switch S 1, S2, S3 and S4; Second switch circuit 310 has switch S 5, S6, S7 and S8; And the 3rd on-off circuit 312 have switch S 9 and S10.
In source electrode driver 300, on draw differential amplifier 302 to have a non-inverting input 302a, an inverting input 302b and an output terminal 302c.Output terminal 302c takes back inverting input 302b.Drop-down differential amplifier 304 has a non-inverting input 304a, an inverting input 304b and an output terminal 304c.Output terminal 304c takes back inverting input 304b.
Fig. 5 is the thin portion circuit diagram of the source electrode driver 300 of the LCD of Fig. 4 embodiment according to the present invention.
In Fig. 5, source electrode driver 300 has comprised and draws differential amplifier 302, one drop-down differential amplifier 304, a voltage clamping circuit 306 and plural number in order to the transistor as switch S 1 to S10 on one.
On draw differential amplifier 302 have one group by N channel metal oxide semiconductor transistor (NMOS) NH3, NH4 formed differential to, one group by P channel metal oxide semiconductor transistor (PMOS) current mirroring circuit that PH1, PH2 formed and a constant current source CR1.On draw the output terminal of differential amplifier 302 to be connected to a P channel metal oxide semiconductor transistor PH3 as output stage.What transistor NH3, NH4 were formed is differential to being electrically connected to the current mirroring circuit that transistor PH1, PH2 are formed individually.More specifically, the drain electrode of transistor PH1 is electrically connected to the drain electrode of transistor NH3, and its source electrode is electrically connected to a high-potential voltage source VDD, with and grid be electrically connected to the grid of transistor PH2; The drain electrode of transistor PH2 is electrically connected to the drain electrode of transistor NH4, and its source electrode is electrically connected to high-potential voltage source VDD, with and grid be electrically connected to its drain electrode.
The grid of transistor NH3 is connected with input end 300a through switch S 1, and is connected with input end 300b through switch S 4.The grid of transistor NH4 is connected to the drain electrode of transistor PH3.The source electrode of transistor NH3, NH4 is connected to the end of a constant current source CR1 jointly, and the other end of constant current source CR1 is connected to low-potential voltage source VSS.
Transistor PH3 is as a charge member, and its source electrode is electrically connected to high-potential voltage source VDD; Its grid is connected to the drain electrode of transistor PH1; With and drain electrode be connected to the source electrode of two P channel metal oxide semiconductor transistor PH4, PH5.The drain electrode of transistor PH4, PH5 is connected to output terminal 300c and 300d respectively, and its grid is connected to control voltage VENA0 and VENB0 respectively.Transistor PH4, PH5 can be by the control of control voltage VENA0 and VENB0 respectively as switch S shown in Figure 45, S6, with optionally will on draw the output terminal V03 of differential amplifier 302 to be electrically connected to output terminal 300c and output terminal 300d via transistor PH3.
Drop-down differential amplifier 304 have one group by P channel metal oxide semiconductor transistor PL3, PL4 formed differential to, one group of current mirroring circuit and constant current source CR2 that is formed by N channel metal oxide semiconductor transistor NL1, NL2.The output terminal of drop-down differential amplifier 304 is connected to a N channel metal oxide semiconductor transistor NL3 as output stage.What transistor transistor PL3, PL4 were formed is differential to being electrically connected to the current mirroring circuit that transistor NL1, NL2 are formed individually.More specifically, the drain electrode of transistor NL1 is electrically connected to the drain electrode of transistor PL3, and its source electrode is electrically connected to a low-potential voltage source VSS, with and grid be electrically connected to the grid of transistor NL2; The drain electrode of transistor NL2 is electrically connected to the drain electrode of transistor PL4, and its source electrode is electrically connected to low-potential voltage source VSS, with and grid be electrically connected to its drain electrode.
The grid of transistor PL3 is connected with input end 300a via switch S 2, and is connected with input end 300b through switch S 3.The grid of transistor PL4 is connected to the drain electrode of transistor NL3.The source electrode of transistor PL3, PL4 is connected to one of constant current source CR2 end jointly, and the other end of constant current source CR2 is connected to high-potential voltage source VDD.
Transistor NL3 is as an arresting element, and its source electrode is electrically connected to low-potential voltage source VSS; Its grid is connected to the drain electrode of transistor NL1; With and drain electrode be connected to the source electrode of two N channel metal oxide semiconductor transistor NL4, NL5.The drain electrode of transistor NL4, NL5 is connected to output terminal 300c and 300d respectively, and its grid is connected to control voltage VENB1 and VENA1 respectively.Transistor NL4, NL5 can be by the control of control voltage VENB1 and VENA1 respectively as switch S shown in Figure 48, S7, optionally the output terminal V04 of drop-down differential amplifier 304 is electrically connected to output terminal 300c and output terminal 300d via transistor NL3.
Voltage clamping circuit 306 has one first sub-clamped circuit, and it is made up of a N channel metal oxide semiconductor transistor NC1 and a P channel metal oxide semiconductor transistor PC1; And one second sub-clamped circuit, it is made up of a N channel metal oxide semiconductor transistor NC2 and a P channel metal oxide semiconductor transistor PC2.Transistor NC1 and PC1 are in order to as source follower, and its source electrode is connected to output terminal 300c jointly; Its grid is connected to control voltage VTL and VTH respectively, in order to the accurate position of the output voltage on strangulation output terminal 300c Vout1 between the first voltage quasi position VA and the second voltage quasi position VB, that is VA≤Vout1≤VB, wherein the first voltage quasi position VA and the second voltage quasi position VB be all greater than low-potential voltage source VSS, and less than high-potential voltage source VDD with and drain electrode be connected to the drain electrode of a P channel metal oxide semiconductor transistor PC3 (also claiming switch S 11) and N channel metal oxide semiconductor transistor NC3 (also claiming switch S 12) respectively.Transistor NC2 and PC2 are in order to as source follower, and its source electrode is connected to output terminal 300d jointly; Its grid is connected to control voltage VTL and VTH respectively, in order to the accurate position of the output voltage on strangulation output terminal 300d Vout2 between the first voltage quasi position VA and the second voltage quasi position VB, that is VA≤Vout2≤VB; With and drain electrode be connected to the drain electrode of a P channel metal oxide semiconductor transistor PC3 and N channel metal oxide semiconductor transistor NC3 respectively.Preferably, transistor NC1 has identical critical voltage with NC2, and transistor PC1 has identical critical voltage with PC2.
For the accurate position of the output voltage on strangulation output terminal 300c, the 300d Vout1, Vout2 between the first voltage quasi position VA and the second voltage quasi position VB, the voltage quasi position of controlling voltage VTL, VTH must meet following formula:
VB＞VTL-Vthn2＞＝VA (1)
VA＜VTH+Vthp2＜＝VB (2)
Wherein Vthn2 is the critical voltage of transistor NC1 and NC2, and Vthp2 is the critical voltage of transistor PC1 and PC2.
In this embodiment, the critical voltage Vthn2 of transistor NC1 and NC2 equals the critical voltage Vthn1 of transistor NH3 and NH4, and the critical voltage Vthp2 of transistor PC1 and PC2 equals the critical voltage Vthp1 of transistor PL3 and PL4; Control voltage VTL equals VA and adds Vthn2 (VTL=VA+Vthn2), and control voltage VTH equals VB and subtracts Vthp2 (VTH=VB-Vthp2).In view of the above, when voltage quasi position scope between between VDD and VB of the accurate position of the output voltage on output terminal 300c, the 300d Vout1, Vout2, transistor PC1, PC2 conducting (source grid voltage Vsg is greater than critical voltage Vthp2), make output voltage accurate position Vout1 and Vout2 respectively via transistor PC1, transistor PC2, and then be discharged to voltage quasi position VB=VTH+Vthp2 with the path of low-potential voltage source VSS through transistor NC3 (if conducting).In addition, when voltage quasi position scope between between VSS and VA of the accurate position of the output voltage on output terminal 300c, the 300d Vout1, Vout2, transistor NC1, NC2 conducting (lock source voltage Vgs is greater than critical voltage Vthn2), make output voltage accurate position Vout1 and Vout2 respectively via transistor NC1, NC2, and then charge to voltage quasi position VA=VTL-Vthn2 with the path of high-potential voltage source VDD through transistor PC3 (if conducting).Moreover, when voltage quasi position scope between between VA and VB of the accurate position of the output voltage on output terminal 300c, the 300d Vout1, Vout2, can conducting because transistor PC1, PC2, NC1, NC2 are neither, so the accurate position of output voltage Vout1, a Vout2 can remain unchanged.
The source electrode of transistor PC3 and NC3 is connected to high-potential voltage source VDD and low-potential voltage source VSS respectively, and its grid is connected to anti-phase each other control voltage VPREB and VPRE respectively.
Should be appreciated that, on draw differential amplifier 302 in order at the accurate position of output voltage Vout1, the Vout2 that improve between the voltage quasi position of voltage quasi position VA and high-potential voltage source VDD on output terminal 300c, the 300d; And drop-down differential amplifier 304 is in order to the accurate position of output voltage Vout1, Vout2 on reduction output terminal 300c, 300d between the voltage quasi position of voltage quasi position VB and low-potential voltage source VSS.
Fig. 6 A and Fig. 6 B in order to the source electrode driver 300 of key diagram 5 (cooperate with reference to figure 4) in the one scan line time with Vout1, Vout2 the specific embodiment that is not urged to level voltage quasi position Vin1, Vin2 in the accurate position of output voltage.Fig. 6 A is in order to conducting (ON) state and disconnection (OFF) state of explanation one scan line time (t0 to t4) interior switch S 1 to S12.Fig. 6 B is in order to the variation of explanation output voltage accurate position Vout1, Vout2 voltage quasi position value in this sweep trace time (t0 to t4).In this specific embodiment, suppose that the level voltage quasi position Vin1 that two input end 300a, 300b are received, the value of Vin2 are respectively V1 and VDD, and the value of the accurate position of the output voltage on two output terminal 300c, the 300d Vout1, Vout2 is respectively VSS and V2.Hereinafter will illustrate source electrode driver 300 in this sweep trace in the time with the value of the accurate position of output voltage Vout1, Vout2 by VSS and V2 operation steps that is not urged to V1 and VDD.
At first, at time t0 during to t1, control voltage VPRE is a high potential state, control voltage VPREB is a low-potential state, make transistor PC3 and NC3 (switch S 11, S12) conducting respectively, and make rest switch S1 to S10 disconnect, so make voltage clamping circuit 306 can be enabled (enable), and with the value strangulation of the accurate position of output voltage Vout1, Vout2 between voltage quasi position VA and voltage quasi position VB.During this, voltage clamping circuit 306 is pulled to VA with the value VSS of the accurate position of the output voltage on output terminal 300c Vout1; In addition, because the value V2 of the accurate position of output voltage Vout2 is positioned between (being clamped to) voltage quasi position VA and voltage quasi position VB, therefore remain unchanged.
Then, when time t1 to t2, switch S 1, S3 conducting, control voltage VENA1, VENB0 are a high potential state, control voltage VENA0, VENB1 are a low-potential state, make transistor PH4 (switch S 5) and transistor NL5 (switch S 7) conducting, and make rest switch disconnect.During this, voltage clamping circuit 306 is by not activation (disable), to remove the accurate position of strangulation output voltage Vout1, Vout2; On draw the grid (non-inverting input) of the transistor NH3 of differential amplifier 302 to receive the level voltage quasi position Vin1 (its value is V1) of input end 300a, and the grid of transistor NH4 (inverting input) receives the accurate position of the output voltage Vout1 (its value is VA) of output terminal 300c; For on draw for the differential amplifier 302, because the voltage quasi position value V1 on the non-inverting input is greater than the voltage quasi position value VA on the inverting input, draw on therefore differential amplifier 302 can be via transistor PH3, PH4 the value of the accurate position of the output voltage Vout1 of output terminal 300c to be improved toward V1 by VA.Simultaneously, the grid (non-inverting input) of the transistor PL3 of drop-down differential amplifier 304 receives the level voltage quasi position Vin2 (its value is VDD) of input end 300b, and the grid of transistor PL4 (inverting input) can receive the accurate position of the output voltage Vout2 (its value is V2) of output terminal 300d; For drop-down differential amplifier 304, because the voltage quasi position value VDD on the non-inverting input is greater than the voltage quasi position value V2 on the inverting input, therefore drop-down differential amplifier 304 can not move, and promptly the value V2 of the accurate position of the output voltage of output terminal 300d Vout2 remains unchanged.
Then, when time t2 to t3, switch S 2, S4 conducting; Control voltage VENA1, VENB0 are a low-potential state, and control voltage VENA0, VENB1 are a high potential state, make transistor PH5 (switch S 6) and transistor NL4 (switch S 8) conducting, and make rest switch disconnect.During this, on draw the grid (non-inverting input) of the transistor NH3 of differential amplifier 302 to receive the level voltage quasi position Vin2 (its value is VDD) of input end 300b, and the grid of transistor NH4 (inverting input) receives the accurate position of the output voltage Vout2 (its value is V2) of output terminal 300d; For on draw for the differential amplifier 302, because the voltage quasi position value VDD on the non-inverting input is greater than the voltage quasi position value V2 on the inverting input, draw on therefore differential amplifier 302 can be via transistor PH3, PH5 the value of the accurate position of the output voltage Vout2 of output terminal 300d to be improved toward VDD by V2.Simultaneously, the grid (non-inverting input) of the transistor PL3 of drop-down differential amplifier 304 receives the level voltage quasi position Vin1 (its value is V1) of input end 300a, and the grid of transistor PL4 (inverting input) can receive the accurate position of the output voltage Vout1 (its value also is V1) of output terminal 300c; For drop-down differential amplifier 304, because the voltage quasi position on the non-inverting input equals the voltage quasi position on the inverting input, therefore drop-down differential amplifier 304 can not move, and promptly the value V1 of the accurate position of the output voltage of output terminal 300c Vout1 remains unchanged.
At last, when time t3 to t4, only switch S 9 and S10 conducting, and make rest switch disconnect, make input end 300a and 300b be electrically connected to output terminal 300c and 300d respectively.During this, level voltage quasi position Vin1 and Vin2 on input end 300a and the 300b directly are sent to output terminal 300c and 300d, make that the value of output voltage accurate position Vout1 and Vout2 can more accurate V1 of changing into and VDD, this action is called an ancient woman's ornament agate short circuit (gammashort).
Fig. 6 A and Fig. 6 C in order to the source electrode driver 300 of key diagram 5 (cooperate with reference to figure 4) in the one scan line time with Vout1, Vout2 another specific embodiment that is not urged to level voltage quasi position Vin1, Vin2 in the accurate position of output voltage.In this specific embodiment, suppose that the level voltage quasi position Vin1 that two input end 300a, 300b are received, the value of Vin2 are respectively VA and V3, and the value of the accurate position of the output voltage on two output terminal 300c, the 300d Vout1, Vout2 is respectively V1 and VDD.Fig. 6 C is in order to the variation of accurate Vout1, Vout2 voltage quasi position value in this sweep trace time (t0 to t4) of the output voltage that this specific embodiment is described.
At first, at time t0 during to t1, only switch S 11, S12 conducting.During this, voltage clamping circuit 306 can be pulled to VB with the value VDD of the accurate position of the output voltage on output terminal 300d Vout2; In addition, because the value V1 of the accurate position of output voltage Vout1 has been positioned between voltage quasi position VA and voltage quasi position VB, therefore remain unchanged.
Then, when time t1 to t2, only switch S 1, S3, S5, S7 conducting.During this, voltage clamping circuit 306 is by not activation (disable), to remove the accurate position of strangulation output voltage Vout1, Vout2; On draw the grid (non-inverting input) of the transistor NH3 of differential amplifier 302 to receive the level voltage quasi position Vin1 (its value is VA) of input end 300a, and the grid of transistor NH4 (inverting input) receives the accurate position of the output voltage Vout1 (its value is V1) of output terminal 300c; For on draw for the differential amplifier 302, because the voltage quasi position value VA on the non-inverting input is less than the voltage quasi position value V1 on the inverting input, therefore draw differential amplifier 302 can not move on, promptly the value V1 of the accurate position of the output voltage of output terminal 300c Vout1 remains unchanged.Simultaneously, the grid (non-inverting input) of the transistor PL3 of drop-down differential amplifier 304 receives the level voltage quasi position Vin2 (its value is V3) of input end 300b, and the grid of transistor PL4 (inverting input) receives the accurate position of the output voltage Vout2 (its value is VB) of output terminal 300d: for drop-down differential amplifier 304, because the voltage quasi position value V3 on the non-inverting input is greater than the voltage quasi position value VB on the inverting input, therefore drop-down differential amplifier 304 can not move, and promptly the value VB of the accurate position of the output voltage of output terminal 300d Vout2 remains unchanged.
Then, when time t2 to t3, only switch S 2, S4, S6, S8 conducting.During this, on draw the grid (non-inverting input) of the transistor NH3 of differential amplifier 302 to receive the level voltage quasi position Vin2 (its value is V3) of input end 300b, and the grid of transistor NH4 (inverting input) receives the accurate position of the output voltage Vout2 (its value is VB) of output terminal 300d; For on draw for the differential amplifier 302, because the voltage quasi position value V3 on the non-inverting input is greater than the voltage quasi position value VB on the inverting input, draw on therefore differential amplifier 302 can be via transistor PH3, PH5 the value of the accurate position of the output voltage Vout2 of output terminal 300d to be improved toward V3 by VB.Simultaneously, the grid (non-inverting input) of the transistor PL3 of drop-down differential amplifier 304 receives the level voltage quasi position Vin1 (its value is VA) of input end 300a, and the grid of transistor PL4 (inverting input) can receive the accurate position of the output voltage Vout1 (its value also is V1) of output terminal 300c; For drop-down differential amplifier 304, because the voltage quasi position on the non-inverting input is less than the voltage quasi position on the inverting input, therefore drop-down differential amplifier 304 can be via transistor NL3, NL4 reduces by V1 the value of the accurate position of the output voltage Vout1 of output terminal 300c toward VA.
At last, when time t3 to t4, only switch S 9 and S10 conducting makes input end 300a and 300b be electrically connected to output terminal 300c and 300d respectively.During this, level voltage quasi position Vin1 and Vin2 on input end 300a and the 300b directly are sent to output terminal 300c and 300d, make that the value of output voltage accurate position Vout1 and Vout2 can more accurate VA of changing into and V3.
Because between the VB to VDD and have enough voltage differences between the VA to VSS, therefore when needing to drive accurate of output voltage, just reach easily than prior art to VDD or VSS, and unrestricted in less driving scope.
Fig. 7 is another alternate embodiment of the source electrode driver of Fig. 5, represents with identical label with Fig. 5 components identical, repeats no more.The difference of Fig. 7 and Fig. 5 be to increase by one group by N channel metal oxide semiconductor transistor NH1, NH2 formed differential to, one group by P channel metal oxide semiconductor transistor PL1, PL2 formed differential right; Switch S 1, S2 are replaced by N channel metal oxide semiconductor transistor NH6, NH7 respectively, and switch S 3, S4 are replaced by P channel metal oxide semiconductor transistor PL6, PL7 respectively.
The drain electrode of transistor NH1, NH2 is electrically connected to the drain electrode of transistor PH1, PH2 respectively, and its source electrode then is electrically connected to the drain electrode of transistor NH7 jointly.The grid of transistor NH2, NH4 is electrically connected to the drain electrode of transistor PH5, PH4 respectively.The source electrode of transistor NH3, NH4 is electrically connected to the drain electrode of transistor NH6 jointly.The source electrode of transistor NH6, NH7 is electrically connected to the ㄧ end of constant current source CR1, and the other end of constant current source CR1 is connected to low-potential voltage source VSS; Its grid is connected to control voltage VENA1 and VENB1 respectively.Control voltage VENA1 and VENB1 are with controlling the activation (enable) or the not activation (disable) of drawing differential amplifier 302 and drop-down differential amplifier 304 respectively.
The drain electrode of transistor PL1, PL2 is electrically connected to the drain electrode of transistor NL1, NL2 respectively, and its source electrode then is electrically connected to the drain electrode of transistor PL7 jointly.The grid of transistor PL2, PL4 is electrically connected to the drain electrode of transistor NL4, NL5 respectively.The source electrode of transistor PL3, PL4 is electrically connected to the drain electrode of transistor PL6 jointly.The source electrode of transistor PL6, PL7 is electrically connected to the ㄧ end of constant current source CR2, and the other end of constant current source CR2 is connected to high-potential voltage source VDD; Its grid is connected to control voltage VENA0 and VENB0 respectively.Control voltage VENA0 and VENB0 are with controlling the activation (enable) or the not activation (disable) of drawing differential amplifier 302 and drop-down differential amplifier 304 respectively.
The grid of transistor NH1 and transistor PL3 is electrically connected to the level voltage quasi position Vin1 on the input end 300a jointly, and the grid of transistor NH3 and transistor PL1 is electrically connected to the level voltage quasi position Vin2 on the input end 300b jointly.
The explanation of the motion mechanism of Fig. 7 such as Fig. 6 A to Fig. 6 C repeats no more.
Fig. 8 is another alternate embodiment of the source electrode driver of Fig. 7, represents with identical label with Fig. 7 components identical, repeats no more.The difference of Fig. 8 and Fig. 7 is that transistor PC3, NC3 are replaced by switch S 11, S12 respectively, and switch S 11 electrically connects the drain electrode of transistor PH4 and the source electrode of transistor NC1, the drain electrode of switch S 12 electric connection transistor PH5 and the source electrode of transistor NC2.The drain electrode of transistor NC1, NC2 is electrically connected to high-potential voltage source VDD, and the drain electrode of transistor PC1, PC2 is electrically connected to low-potential voltage source VSS.
The motion mechanism of Fig. 8 repeats no more as the explanation of 6A to 6C figure.
According to above explanation, the driven scope of source electrode driver 300 of the present invention can't be subjected to the restriction as prior art, and owing to increased the driven scope, solves the problem of known technology by this.
Moreover because a plurality of data lines can share and draw on one and a drop-down differential amplifier 302,304, so the size of source electrode drive circuit can be reduced, and circuit manufacturing cost thereby be lowered.
Should be appreciated that though have two groups of input ends and output terminal according to the source electrode driver 300 of the embodiment of the invention, in order to drive two data lines, it also can only have one group, in order to drive a data line; Perhaps, if the one scan line time is enough long, the source electrode driver 300 of the embodiment of the invention also can have many groups input end and the output terminals more than surpassing two groups, and the switching in turn with by on-off circuit drives a plurality of data lines.
Though the present invention discloses with previous embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention, and when doing various changes and modification.Therefore protection scope of the present invention is as the criterion when looking described the claim scope person of defining.
Claims (17)
1. a source electrode driver is characterized in that, comprises:
One first differential circuit has an input end in order to receiving one first input signal, with an output terminal in order to according to this first input signal, produce one first output signal; And
One first voltage clamping circuit has the output terminal that an input end couples this first differential circuit, in order to this first output signal of strangulation between one first voltage quasi position and one second voltage quasi position;
Wherein, this first differential circuit is coupled to a high-potential voltage source, and the voltage quasi position in this high-potential voltage source is greater than this first voltage quasi position and this second voltage quasi position.
2. source electrode driver as claimed in claim 1 is characterized in that other comprises:
One first on-off circuit couples this first differential circuit; And
One second differential circuit couples this first on-off circuit;
Wherein this this first input signal of first on-off circuit selectivity conducting to this first differential circuit or this first input signal of conducting to this second differential circuit.
3. source electrode driver as claimed in claim 2 is characterized in that other comprises:
One second switch circuit couples this first differential circuit and this second differential circuit;
Wherein when this this first input signal of first on-off circuit conducting during to this first differential circuit, then this second switch circuit turn-on one second input signal is to this second differential circuit.
4. source electrode driver as claimed in claim 1 is characterized in that other comprises:
One first on-off circuit couples this first differential circuit; And
One second differential circuit couples this first on-off circuit, and this second differential circuit has an output terminal;
The wherein output terminal of the input end of the output terminal of this this first differential circuit of first on-off circuit selectivity conducting and this first voltage clamping circuit or this second differential circuit of conducting and the input end of this first voltage clamping circuit.
5. source electrode driver as claimed in claim 4 is characterized in that other comprises:
One second voltage clamping circuit has an input end;
One second switch circuit couples this second differential circuit and this second voltage clamping circuit;
Wherein when the input end of the output terminal of this this first differential circuit of first on-off circuit conducting and this first voltage clamping circuit, the input end of the output terminal of this this second differential circuit of second switch circuit turn-on and this second voltage clamping circuit then.
6. source electrode driver as claimed in claim 1 is characterized in that, this first voltage clamping circuit comprises one first on-off circuit in addition, in order to this first voltage clamping circuit of selectively enabling.
7. source electrode driver as claimed in claim 1 is characterized in that, other comprises one first on-off circuit, connects the input end and the output terminal of this driver in order to selectivity.
8. source electrode driver as claimed in claim 1 is characterized in that, other comprises one first on-off circuit, couples this first differential circuit, wherein this this first differential circuit of first on-off circuit selectively enabling.
9. source electrode driver as claimed in claim 8 is characterized in that other comprises:
One second switch circuit; And
One second differential circuit couples this second switch circuit;
Wherein when this this first differential circuit of first on-off circuit activation, this this second differential circuit of not activation of second switch circuit then.
10. source electrode driver as claimed in claim 1 is characterized in that this driver applications is in a liquid crystal indicator.
11. source electrode driver as claimed in claim 1 is characterized in that, other comprises a multi-level voltage generation circuit, couples this first differential circuit.
12. the driving method of a source electrode driver is characterized in that, comprises the following step:
First output signal of strangulation one first differential circuit output is between one first voltage quasi position and one second voltage quasi position; And
According to this first output signal and an input signal, produce one second output signal, and with this second output signal as this first output signal;
Wherein, this first differential circuit is coupled to a high-potential voltage source, and the voltage quasi position in this high-potential voltage source is greater than this first voltage quasi position and this second voltage quasi position.
13. driving method as claimed in claim 12 is characterized in that, other comprises the following step: first output signal of removing this first differential circuit output of strangulation.
14. driving method as claimed in claim 12 is characterized in that, other comprises the following step: this second output signal is improved toward this input signal.
15. driving method as claimed in claim 12 is characterized in that, other comprises the following step: this second output signal is reduced toward this input signal.
16. driving method as claimed in claim 12 is characterized in that, other comprises the following step: drive a liquid crystal indicator with this second output signal.
17. driving method as claimed in claim 12 is characterized in that, other comprises the following step: produce a multi-level voltage as this input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510009400XA CN100389449C (en) | 2005-02-18 | 2005-02-18 | Source driver and its driving method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510009400XA CN100389449C (en) | 2005-02-18 | 2005-02-18 | Source driver and its driving method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1822085A CN1822085A (en) | 2006-08-23 |
| CN100389449C true CN100389449C (en) | 2008-05-21 |
Family
ID=36923418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200510009400XA Expired - Fee Related CN100389449C (en) | 2005-02-18 | 2005-02-18 | Source driver and its driving method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100389449C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101149907B (en) * | 2006-09-18 | 2012-04-11 | 奇景光电股份有限公司 | Liquid crystal display possessing source cathode drive and data transmission method |
| CN101354877B (en) * | 2007-07-25 | 2012-03-21 | 联咏科技股份有限公司 | Source electrode driver with electric charge share |
| CN101471577B (en) | 2007-12-29 | 2011-06-15 | 比亚迪股份有限公司 | Voltage balance circuit for double-burl chargeable battery |
| CN101471602B (en) | 2007-12-29 | 2012-11-07 | 比亚迪股份有限公司 | Bidirectional DC power supply circuit |
| JP4825838B2 (en) * | 2008-03-31 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | Output amplifier circuit and display device data driver using the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5237212A (en) * | 1991-01-16 | 1993-08-17 | Sony Corporation | Level converting circuit |
| US5623279A (en) * | 1993-09-10 | 1997-04-22 | Kabushiki Kaisha Toshiba | Capacitive load driving circuit including input selection circuit and liquid crystal display device using the driving circuit |
| CN1389842A (en) * | 2001-06-04 | 2003-01-08 | 精工爱普生株式会社 | Operational amplifying circuit, driving circuit and driving method |
| US6567327B2 (en) * | 2000-08-10 | 2003-05-20 | Nec Corporation | Driving circuit, charge/discharge circuit and the like |
| US20030146788A1 (en) * | 2002-02-04 | 2003-08-07 | Seiko Epson Corporation | Operation amplifier circuit, drive circuit and method of controlling operation amplifier circuit |
-
2005
- 2005-02-18 CN CNB200510009400XA patent/CN100389449C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5237212A (en) * | 1991-01-16 | 1993-08-17 | Sony Corporation | Level converting circuit |
| US5623279A (en) * | 1993-09-10 | 1997-04-22 | Kabushiki Kaisha Toshiba | Capacitive load driving circuit including input selection circuit and liquid crystal display device using the driving circuit |
| US6567327B2 (en) * | 2000-08-10 | 2003-05-20 | Nec Corporation | Driving circuit, charge/discharge circuit and the like |
| CN1389842A (en) * | 2001-06-04 | 2003-01-08 | 精工爱普生株式会社 | Operational amplifying circuit, driving circuit and driving method |
| US20030146788A1 (en) * | 2002-02-04 | 2003-08-07 | Seiko Epson Corporation | Operation amplifier circuit, drive circuit and method of controlling operation amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1822085A (en) | 2006-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4328306B2 (en) | Source driver and source driving method | |
| US7081786B2 (en) | Level shifter and flat panel display | |
| US20160125955A1 (en) | Shift Register, Driving Method Thereof and Gate Driving Circuit | |
| KR101989721B1 (en) | Liquid crystal display device and gate driver thereof | |
| US20090051639A1 (en) | Method and device for reducing voltage stress at bootstrap point in electronic circuits | |
| US8289053B2 (en) | Comparator circuit and display device provided with the same | |
| EP2259268A2 (en) | Semiconductor device | |
| CN100389449C (en) | Source driver and its driving method | |
| GB2543235A (en) | Gate electrode drive circuit based on IGZO process | |
| US8648849B2 (en) | Buffer circuit | |
| US8884865B2 (en) | Scanning line driving circuit, display device, and scanning line driving method | |
| CN109658888A (en) | Shift register cell, driving method, gate driving circuit and display device | |
| KR20050033767A (en) | A circuit and method for sampling and holding current, de-multiplexer and display apparatus using the same | |
| CN111429830B (en) | Shifting register unit, driving method thereof, grid driving circuit and display panel | |
| CN100505017C (en) | Converting voltage level circuit and method | |
| TWI415083B (en) | A semiconductor integrated circuit and a semiconductor integrated circuit for driving a liquid crystal display | |
| CN101303838A (en) | Systems for displaying images by utilizing vertical shift register circuit to generate non-overlapped output signals | |
| CN109686332B (en) | Compensation module, logic gate circuit, gate drive circuit and display device | |
| US7852976B2 (en) | Bidirectional controlling device for increasing resistance of elements on voltage stress | |
| US7388403B1 (en) | Two-stage level shifting module | |
| EP2536023A2 (en) | Method and apparatus for biasing rail to rail DMOS amplifier output stage | |
| CN110728960A (en) | LCD drive circuit and display device | |
| CN110322828B (en) | Pixel driving circuit, driving method thereof and display device | |
| CN108022549B (en) | Logic circuit, shift register, drive circuit and display panel | |
| CN101304240B (en) | Voltage limiting apparatus as well as operation amplifier applying the same and circuit design method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080521 Termination date: 20190218 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |