JP2833070B2 - Track / hold circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of distortion of a hold waveform generated by a shift in acquisition timing in a track / hold circuit.

<Prior Art> FIG. 7 is a configuration circuit diagram showing a specific example of a conventional track / hold circuit (hereinafter also referred to as a T / H circuit). 1 is a track / hold amplifier (also called T / H amplifier), SW1, S
W2 The first, second FET switch, an output terminal and the FET switch of the C _H is T / H amplifier 1 connected in series between the common potential point and the inverting input terminal of the T / H amplifier (hereinafter referred to as common) SW1, SW2
Hold capacitor connected between the connection point, R ₃ the resistance for damping is connected between the output terminal of the hold capacitor C _H and T / H amplifier 1, SW3, SW4 is the inverting input terminal of the T / H amplifier third, fourth FET switches, input terminals 3 of T / H input voltage V _in is applied to serially connected between the common, R ₁
R ₁ equal value connected between the resistors, R2 is SW3, SW4 said output terminal of the connection point and T / H amplifier 1 connected between a connection point of the input terminal 3 and the FET switches SW3, SW4 are ( (When the gain is 1). Reference numeral 4 denotes an output terminal of the T / H circuit to which the output terminal of the T / H amplifier 1 is connected. FET switches SW1 to SW4
Is composed of D-MOS FET switches, and the gates of SW2 and SW3 are
With the T / H clock, the gates of SW1 and SW4 are driven by the inverted clock. These clocks are generated by an external circuit.

In track mode, FET switches SW2 and SW3 are on, FET
Switches SW1, SW4 are turned off, T / H circuit constitutes the inverting amplifier, the input voltage V _in is output by -1 times the gain.
Hold mode is entered, FET switches SW1 and SW4 are turned on, and FE
When the T switches SW2 and SW3 are turned off, the hold capacitor C _H
Holds the voltage value of the inverted output signal at the timing when SW2 is turned off. Note Since FET switch SW4 is turned on T / H input voltage V _in by the input current flows to the common, T /
It is separated from H output Vout.

<SUMMARY OF THE INVENTION> However, when the frequency of the input signal voltage V _in is higher than the above circuit, the current that charges the hold capacitor C _H is increased, the hold voltage falling caused by ON resistance of the FET switch SW2 The timing of the modulation was modulated, and harmonic distortion occurred in the reproduced waveform.

Hereinafter, this phenomenon will be described in detail. In the T / H circuit of FIG. 7, a D-MOS switch is used for SW2. The D-MOS switch has a capacitance C _gd between the gate and the drain, and the capacitance has voltage dependency. That is, as the gate-drain voltage V _gd increases, C _gd also increases. Current charging the hold capacitor C _H is increased when the frequency of the input signal increases in track mode, a change in the voltage drop occurring in the on-resistance of SW2. The gate voltage is constant at, for example, 5 V, but when the drain voltage changes due to the voltage drop, V _gd changes, and therefore C _gd also changes. If C _gd fluctuates due to a change in the drain voltage, the CR time constant generated between the output resistance of the gate drive circuit of SW2 changes, and SW
The timing at which 1 is turned off, that is, the timing of data acquisition, is modulated. Thus the reproduced signal waveform of the held data becomes one that contains harmonic distortion with respect to the waveform of the input signal V _in. Figure 8 is shows this state, shows a phase relationship (A) is a current flowing through the C _H of the input signal V _in and the track mode I.
(R) indicates a shift in the acquisition timing, and V _gd ,
C _gd is maximized is CR time constant when the maximum, but delayed acquisition timing by Delta] t _1, when the V _gd, is C _gd becomes minimum, becomes CR time constant is the minimum, proceeding acquisition timing by Delta] t ₂ I have. (C) compares the ideal waveform (dotted line: input waveform) with the reproduced waveform (the waveform after A / D conversion of the T / H circuit output), and shows that the reproduced waveform contains harmonic distortion. Have been.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to realize a track / hold circuit in which the timing of data acquisition is not modulated and is constant.

<Means for Solving the Problems> A track / hold circuit according to the present invention performs a track operation and a hold operation of an input signal by using at least an output stage in common, and performs a track operation in which the input signal is connected to an inverted input terminal during the track operation. / Hold amplifier, and one end thereof is connected to the output terminal of the track / hold amplifier, and at least the other end is connected to the track / hold amplifier at the time of the hold operation.
A hold capacitor connected to the inverting input terminal of the hold amplifier, a first FET switch connected between the other end of the hold capacitor and common, a capacitor having one end connected to the output terminal of the track / hold amplifier, The second connected between the other end of this capacitor and the common
FET switch, a level shift circuit that inputs a voltage at the other end of the capacitor, and a drive circuit that turns on the first FET switch with an output voltage of the level shift circuit during a track operation. It is characterized by.

<Operation> In the track mode, the potential of the gate terminal of the FET switch changes equal to the potential of the drain terminal of the FET switch by the level shift circuit and the driving circuit.
The voltage and capacitance between the gate and drain of the switch are constant. Therefore, the data acquisition timing is also constant.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an inversion type track / hold circuit according to a first embodiment of the present invention. Here, the same parts as those in FIG. 7 are denoted by the same symbols, and the description is omitted. C ₁ is
The second capacitor, SW5 fifth D-MOS FET switch for monitor connected between the other end and the common capacitor C _1, 5 is FET having one end to the output terminal of the T / H amplifier 1 is connected
A level shift circuit for inputting the voltage of the drain terminal of the switch SW5 and shifting the voltage by 5 V. Reference numeral 6 designates an output voltage of the level shift circuit 5 as a TTL level power supply voltage. ) Is a D-type flip-flop (A-CMOS) driven by a clock synchronized with the above. The gate of the FET switch SW2 is driven by the output of the flip-flop 6, and the gate of SW5 is always on with 5V applied. FET switches SW2 and SW5, characteristics of the capacitor C _H and C ₁ is used as equal to each other.

The operation of the track / hold circuit having the above configuration will be described below. In track mode, FET switches SW2 and S
W3 is turned on, the input signal V _in and sign as T / H output is equal to that of signal is outputted in reverse. In this case the current I charges the hold capacitor C _H flows through the FET switch SW2, FET
The drain voltage of switch SW2 is its ON resistance (several 100Ω)
Fluctuates due to the voltage drop due to Since C _H and C ₁ and SW 2 and SW 5 are elements having the same characteristics, the drain voltage of the FET switch SW 5 changes exactly the same as that of SW 2. The drain voltage of the FET switch SW5 is + 5V shifted by the level shift circuit 5, from the level shift circuit 5 AC signal + 5V centers are supplied to the power supply terminal V _SS of the flip-flop 6. When the output Q of the flip-flop 6 becomes High due to the clock input synchronized with the T / H clock, the output of the level shift circuit 5 is output as it is. When SW2 is on, the potential difference between the gate and the drain of SW2 Is always constant at 5V. When the output of the flip-flop circuit 6 is low, a common level is output and SW2 is turned off. FET in track mode as above
Since V _{gd of} switch SW2 is constant, C _{gd of} FET switch SW2 is
Becomes constant, the CR time constant at the time of switching becomes constant, and the timing of data acquisition becomes constant regardless of the input signal.

FIG. 2 shows a first modification of the track / hold circuit shown in FIG. The difference from FIG. 1 is that the level shift circuit 5
Instead of supplying the output of
The difference is that the power is supplied to the power supply of the differential switch 7.
The output of the D-type flip-flop 6 driven by the clock is the switching input of the differential switch 7. Here, a delay corresponding to the switching of the differential switch 6 with respect to the T / H clock occurs in the ON / OFF signal of SW2, but there is no problem if the overall timing is adjusted. As shown by the dotted line in FIG. 2, the external circuit can be simplified by setting the Q output and the inverted output of the flip-flop circuit 6 as the inverted output of the T / H output and the T / H output, respectively.

FIG. 3 is a circuit diagram showing a second modification of the track / hold circuit of FIG. 1, in which the input of the level shift circuit 5 is directly taken from the drain terminal of SW2. This can be realized if the level shift circuit 5 is an ideal one that does not affect the T / H circuit 6, that is, if the input impedance ≒ ∞ and the bias current ≒ 0. Circuit is simplified can be omitted capacitors C ₁ and FET switch SW5,
FET switches SW2 and SW5, the error does not occur due to mismatching between the capacitor C _H and C _1.

FIG. 4 shows a second example of the track / hold circuit according to the present invention.
FIG. 4 is a configuration circuit diagram showing a non-inverting type in the embodiment of FIG. 1 are given the same symbols. A T / H 10 has two input stages 101 and 102 and an output stage to which the output is connected, and selects one of the input stages 101 and 102 by switching an operating current supplied to the input stages 101 and 102.
In the amplifier, the input signal V _in is applied to the non-inverting input terminal of the first input stage 101, the inverting input terminal is connected to the output terminal of the output stage 103. Here, the first stage of the input stages 101 and 102 is constituted by a differential circuit of FET. Hold capacitor _CH is second
Input stage 102 and the output stage 103 of the T / H amplifier 10.
Connected between the output terminal, the damping resistor R ₃ inserted between the hold capacitor C _H and the output stage 103, the operation FET switch SW2 is connected between the inverting input terminal of the input stage 102 and the common The on / off operation is controlled in conjunction with the switching of the current. SW6 is connected between the non-inverting input terminal and the common input stage 102, FET switch whose on-off is controlled in conjunction with SW2, identical to the hold capacitor C _H to C ₂ is connected in parallel with the FET switch SW6 Capacitor of capacity, FE
T switch SW2 is for compensating the pedestal voltage generated at the time of switching, and 11 is connected to a negative voltage source _VS- at one end, and is a constant for supplying operating current to input stage 101 or 102 of T / H amplifier 10. Current source 2, the other end of the constant current source 11 is the input stage
This is a current switch that is connected by switching to either 101 (T side) or 102 (H side).

The bootstrap circuit is the same as in the case of FIG.
5V drain voltage of switch SW5 by level shift circuit 5
After (TTV For Level) level shifting, and it supplies its output to the power supply V _SS of the flip-flop 6, and drives the flip-flop circuit 6 with a clock that is synchronized with T / H clock,
The switches SW2 and SW6 are driven by the output of the flip-flop circuit 6.

 Next, the operation will be described.

(A) In the track mode In the track mode, in FIG.
W2 and SW6 are turned on, and the current switch 2 is connected to the T side. Input signal Vin passes through the track amplifier gain 1 that combines an output stage 103 and the input stage 101, the input signal V _in and magnification of T
The / H output appears at 4. In this case the current I charges the hold capacitor C _H flows through the FET switch SW2, the drain voltage of the FET switch SW2 is varied by a voltage drop due to the on resistance (several 100 [Omega). Since C _H and C ₁ and SW 2 and SW 5 have the same characteristics, the drain voltage of the FET switch SW 5 is also SW.
Exactly the same change as the drain voltage of 2. As a result, as in the case of FIG. 1, the gate-drain voltage V _gd becomes constant (here, 5 V).

(B) In the hold mode In the hold mode, the switches SW2, SW2,
SW6 is turned off, and the current switch 2 falls to the H side. Switch S
W2 is the voltage value of the AC signal at that time the hold capacitor C _H is turned off (input signal) is held.

That is, as described in (a), since the gate-drain voltage of SW2 is constant, the gate-drain capacitance C _{gd of} SW2 is constant, and the change of the hold timing caused by the change of the switching time constant is eliminated. Waveform distortion can be reduced.

FIG. 5 is a diagram showing the frequency characteristics of the number of effective bits obtained by experiments on the track / hold circuit.
The accuracy is improved over the entire frequency band as compared with the conventional example.

FIG. 6 shows the frequency characteristics of the second harmonic distortion obtained by experiments on the above track / hold circuit. It can be seen that the harmonic distortion is significantly improved in the high frequency range.

In the non-inverting track / hold circuit of FIG. 4, the output of the level shift circuit 5 may be connected to the power supply of the differential switch 7 as in the case of FIG.

In the non-inverting track / hold circuit of FIG. 4, the voltage at the drain terminal of SW2 may be directly fed back by the bootstrap circuit via an amplifier having a high input impedance as in the case of FIG.

Further, in the track / hold circuits of the above embodiments, at least the output stage is commonly used, so that the AC amplitude applied to the FET switch SW2 is relatively small, and this can be further reduced by the bootstrap circuit. It is particularly effective when used in converters. Also, the configuration is simplified.

<Effects of the Invention> As is clear from the above description, according to the present invention,
By canceling the voltage drop due to the switch-on resistance by the bootstrap circuit, it is possible to realize a track / hold circuit having a fixed data acquisition timing without modulation and having a simple configuration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a track / hold circuit according to the present invention. FIG. 2 is a circuit diagram showing a first modification of the track / hold circuit according to the present invention. FIG. 4 is a circuit diagram showing a second modification of the track / hold circuit according to the present invention. FIG. 4 is a circuit diagram showing a second embodiment of the track / hold circuit according to the present invention.
FIGS. 6 and 7 are characteristic curves of the track / hold circuit of FIG. 4, FIG. 7 is a circuit diagram showing a conventional track / hold circuit, and FIG. 8 is for explaining the operation of the apparatus of FIG. FIG. 1,10 ... Track / hold amplifier, 4 ... Output terminal,
5 ... level shift circuit, 6 ... D flip-flop,
7 ...... differential switch, 103 ...... output stage, C _H ...... hold capacitor, SW2 ...... FET switch, V _in ...... input voltage.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/00-1/88 G11C 27/02

Claims (1)

(57) [Claims] 1. A track / hold amplifier for performing a track operation and a hold operation of an input signal by using at least a common output stage and connecting the input signal to an inverting input terminal during the track operation, and an output terminal of the track / hold amplifier. And a first FET switch connected between the other end of the hold capacitor and the common, the other end being connected to the inverting input terminal of the track / hold amplifier at least during the hold operation. A capacitor having one end connected to the output terminal of the track / hold amplifier, and a second FE connected between the other end of the capacitor and common.
A T switch, a level shift circuit that inputs a voltage at the other end of the capacitor, and a drive circuit that turns on the first FET switch with an output voltage of the level shift circuit during a track operation. Characterized track / hold circuit.