JP2817268B2 - Track hold circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of distortion of a hold waveform generated due to a shift in timing of holding an input signal in a track hold circuit.

<Prior Art> FIG. 6 is a configuration circuit diagram showing a specific example of a conventional track and hold circuit (hereinafter referred to as a T / H circuit).

1 has two input stages 11 and 12 and an output stage to which the output thereof is connected, and selects one of the input stages 11 and 12 by switching the operating current supplied to the input stages 11 and 12. in H amplifier, the input signal V _in is applied to the non-inverting input terminal of the first input stage 11, inverting input terminal is connected to the output terminal of the output stage 13. Here, the first stage of the input stages 11 and 12 is configured by an FET differential circuit. CH is connected between the inverting hold capacitor connected between an output terminal of the input terminal and the T / H amplifier 1 of the output stage 13, R is the output stage and the hold capacitor C _H of the second input stage 12 Depending on frequency with resistance
Shall be inserted to operate stably even if the impedance variation of the C _H, SW1 is interlocked with the on-off and control the connected switching the operating current between the common potential point and the inverting input terminal of the input stage 12 FET switch that is, SW2 is connected between the common potential point and the non-inverting input terminal of the input stage 12, the FET switch that turned on and off in conjunction with SW1 is controlled, C ₁ is FET
A capacitor with the same capacity as the hold capacitor connected in parallel with the switch SW2, for compensating the pedestal voltage generated when the FET switch SW1 is switched,
An input stage 3 of the T / H amplifier 1 has one end connected to the negative voltage source _VS-.
Or, a constant current source 2 for supplying an operating current to 12 is a current switch for connecting the other end of the constant current source 3 to one of the input stages 11 (T side) and 12 (H side) by switching. . T / H
Is a switch control signal.

 Next, the operation will be described.

(A) At the time of the track mode In the track mode, the FET switches SW1 and SW2 are turned on, the current switch 2 is tilted to the T side, and the operating current selectively flows through the input stage 11. The input signal Vin is output through a track amplifier having a gain of 1 _{in which} the input stage 11 and the output stage 13 are combined.

(B) In the hold mode In the hold mode, the switches SW1 and SW1 are at the same timing.
SW2 is turned off, and the current switch 2 falls to the H side. Switch S
W1 is a voltage value of the AC signal at that time the hold capacitor C _H is turned off (input signal) is held.

In the circuit, however the <SUMMARY invention>, when the frequency of the input signal V _in increases in the track mode, the current for charging the hold capacitor C _H is increased, the voltage drop across the on-resistance of the FET switch SW1 As a result, the drain voltage of the FET switch varies. Since this drain voltage is applied to the gate terminal of the inverting input side FET of the input stage 12, the capacitance C _gd between the gate and drain of this first stage FET varies. It has been experimentally confirmed that the timing of holding when switching from the track mode to the hold mode is modulated due to the fluctuation of the capacitance C _gd , and harmonic distortion occurs in the reproduced waveform.

The present invention has been made to solve the above-described problem, and has as its object to realize a track-and-hold circuit in which the hold timing is constant without being modulated.

<Means for Solving the Problems> The present invention provides an amplifier having two input stages and switching one of the two input stages by switching an operating current supplied to these input stages, and an amplifier having the same. A hold capacitor connected between one input stage and the output of the amplifier, and a switch connected to the operating current connected between a side of the hold capacitor connected to one input stage of the amplifier and a common potential point. And a switch whose on / off is controlled, and a track / hold circuit for applying an input signal to be held to the other input stage of the amplifier. Equipped with a bootstrap circuit that feeds back a signal based on the voltage at the connection point to the drain terminal of the first-stage FET of the input stage to which the hold capacitor connects. The point is that the potential difference between the drain and the gate of the FET is configured to be kept constant in the track mode.

<Operation> In the track mode, since the potential difference between the drain and the gate of the first-stage FET of one input stage is kept constant, the capacitance between the drain and the gate becomes constant and the hold timing is not modulated.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration circuit diagram showing one embodiment of a track hold circuit according to the present invention. Here, the same parts as those in FIG. 6 are denoted by the same symbols, and the description is omitted. In the voltage monitor circuit 4 for monitoring the drain voltage of the FET switch SW1, C ₂
Is a capacitor having the same capacitance as the hold capacitor C _H and having one end connected to the output terminal of the T / H amplifier 1, SW3 having the same characteristics as SW1 and being connected between the other end of the capacitor C ₂ and the common potential point, Reference numeral 5 denotes a buffer amplifier having a gain of 1, which transmits a voltage change at the drain terminal of the FET switch SW3 to the input stage 12a. 5V (TTL level high level) is applied to the gate terminal of FET switch SW3, and it is always on.

FIG. 2 is a main part configuration circuit diagram showing details of the input stage 12a. J ₁ and J ₂ are differential FET pairs of the input stage 12a whose source terminals are connected to the H-side selection terminal of the current switch 2 and use a junction type here, and 121 and 122 have one end connected to a positive voltage source V _{S +} The constant current sources Q ₁ and Q ₂ are connected to the transistors whose emitter terminals are connected to the drain terminals of the FETs J ₁ and J ₂ , respectively, and whose base terminals are connected to the other ends of the constant current sources 121 via resistors. pair, R2 is resistance connected between the common potential point and the emitter terminal of the transistor Q1, R ₀ is connected to two resistors between the transistors Q _1, Q ₂ of the collector terminal and a positive voltage source V _{S +,} R ₁ the other end connects one end to the other end of the constant current source 121 is connected to the source terminal of FETJ _1, J ₂ resistors, D _S
Is connected to the cathode terminal of the Schottky diode, D _V is the cathode terminal Schottky diode D _S of the anode terminal connected to the other end of the resistor R ₁ is its cathode terminal connected to the other end of the constant current source 122 Zener diode,
R ₃ is a Zener diode D the anode of the _V terminal and the negative voltage source V
_This is a resistor connected between _S- . The output of the buffer amplifier 5 to the anode terminal of the Zener diode D _V is connected.
In the above configuration, constituting _{Q 1, Q 2, R 2} , R 1, D S, D V, R 3 is a bootstrap circuit 8 to communicate with to have a DC offset voltage fluctuation of the buffer amplifier 5 outputs .

The operation of the track / hold circuit having the above configuration will be described below.

(A) In the track mode In the track mode, in FIG.
W1 and SW2 are turned on, current switch 2 is connected to T side,
Magnification of the signal and the input signal V _in is output as T / H output.
FET switch SW1 at this time flows a current I for charging the hold capacitor C _H, the drain voltage of the FET switch SW1 is varied by a voltage drop due to the on resistance (several 100 [Omega). C _H
And C ₂ , and SW1 and SW3 have the same characteristics.
The drain voltage of the switch SW3 changes exactly the same as the drain voltage of the switch SW1. In FIG. 2, a constant voltage diode D _V
Is set to a voltage higher than the pinch-off voltage of the junction FET, the FETs J ₁ and J ₂ are turned off, and as a result, the transistor Q ₂ is also turned off. A to which the output of the buffer amplifier 5 is added
Voltage variation of the points travels receives DC levels shift constant voltage diode D _V, the Schottky diode D _S the resistor R ₁ to the point B. The emitter of the transistor Q ₁ is are connected between the resistor R ₂ is the common potential point, since here a minute current flows through the transistor Q ₁ is turned on. Therefore FE
The voltage fluctuation at the point A is transmitted to the point C at the drain terminal of the T. The voltage fluctuation of the point A to the source terminal of FETJ ₁ is transmitted. As a result, the gate terminal, the drain terminal, and the source terminal of FETJ ₁ undergo the same voltage fluctuation, and the gate
The drain voltage V _gs and the gate-source voltage V _gd are always constant.

(B) At the time of the hold mode In the hold mode, the current switch 2 is connected to the H side,
In FIG. ₂ , the potentials at the sources of the FET switches J ₁ and J ₂ drop to the potential at the operating point. As a result, the Schottky diode D _S is reverse biased, turned off, the current source 12
The current of 1 flows into the point E. Also similarly to the current track mode of the current source 122, to flow to the resistor R _3, always be current flows in the constant-voltage diode D _V. As described above, in the hold mode, the Schottky diode D _S
Is off, the feedback by the buffer amplifier 5 and the input stage 12a forming the hold amplifier are completely disconnected.

Since the gate-drain voltage V _gd of FETJ ₁ of the input stage 12a in the track mode as described above is fixed FETJ ₁ Gate
Drain capacitance C _gd becomes constant (also V _gs similar), the timing for holding the input V _in is constant regardless the input signal.

FIG. 3 is a graph showing characteristics of the frequency of the effective bit number obtained by an experiment on the track and hold circuit of the above embodiment. The effective bit number is improved over the entire frequency band as compared with the conventional example. The harmonic distortion (second order) is improved by about 6 dBc around 400 kHz.

FIG. 4 shows a second embodiment of the track-hold circuit according to the present invention, which is a combination of the circuit shown in FIG. 1 and a circuit for compensating a change in the capacitance between the gate and drain of the switch SW1 and a harmonic distortion. It is a circuit diagram. The difference from Fig. 1 is the FE
5V drain voltage of T switch SW3 by level shift circuit 6
After (TTL For Level) level shifting, and supplies its output to the power supply V _SS of the flip-flop 7, to drive the flip-flop circuit 7 in clock synchronized with the T / H clock,
The point is that the switches SW1 and SW2 are driven by the output of the flip-flop circuit 7. The change in the drain voltage of the switch SW3 is transmitted to the power supply of the flip-flop circuit 7 by the level shift circuit 6, and the high-level output of the flip-flop circuit 7 similarly changes in the track mode. Therefore, the gate voltage of the switch SW1 fluctuates in the same manner as the drain voltage, so that the gate-drain voltage of the switch SW1 becomes constant. As a result, the gate-drain capacitance C _{gd of} SW1 becomes constant, and it is possible to reduce the waveform distortion due to the change of the hold timing caused by the change of the switching time constant.

FIG. 5 is a diagram showing the frequency characteristic of the number of effective bits obtained by an experiment on the track and hold circuit of FIG.
Compared to FIG. 3, the number of effective bits in the high band (100 kHz or more) is further improved. Harmonic distortion (second order) is about 13 dBc improvement around 400 kHz.

In each of the above embodiments, the configuration can be simplified by connecting the drain terminal of SW1 to an amplifier having a high input impedance and directly feeding back the voltage of the drain terminal of SW1 by the bootstrap circuit.

<Effects of the Invention> As is clear from the above description, according to the present invention,
It is possible to realize a track-and-hold circuit in which the hold timing is constant without being modulated by a simple configuration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a track-hold circuit according to the present invention, FIG. 2 is a circuit diagram showing a main part of an input stage 12a of FIG. 1, and FIG. FIG. 4 is a characteristic curve diagram of the track-hold circuit according to the present invention.
5, FIG. 5 is a characteristic curve diagram of the circuit of FIG. 4, and FIG. 6 is a circuit diagram of a conventional track and hold circuit. 1 ... amplifier, 8 ... bootstrap circuit, 11, 12a ...
… Input stage, C _H … Hold capacitor, SW1… Switch, J ₁ …… First stage FET.

Claims (1)

(57) [Claims] An amplifier having two input stages and selecting one of the two input stages by switching an operating current supplied to these input stages, and one input stage and an output of the amplifier. And a hold capacitor connected between the input side of the hold capacitor connected to one input stage of the amplifier and a common potential point, the on / off of which is controlled in conjunction with the switching of the operating current. And a switch for applying an input signal to be held to the other input stage of the amplifier, wherein one input of the hold capacitor connects a signal based on a voltage at a connection point between the hold capacitor and the switch. It has a bootstrap circuit that feeds back to the drain terminal of the first stage FET, and the potential difference between the drain and gate of the first stage FET is in track mode. A track-and-hold circuit characterized in that it is configured to be kept constant.