JPH03218640A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To make it possible to form an active region having a uniform particle diameter by a method wherein an impurity is introduced in parts, which are used as source and drain regions, of an amorphous semiconductor film and a heat treatment for generating a solid phase crystal growth in the semiconductor film is performed. CONSTITUTION:An impurity is introduced in parts, which are used as source and drain regions 17a, of an amorphous semiconductor film 14 and a heat treatment for generating a solid phase crystal growth in the film 14 is performed. That is, the solid phase crystal growth in the regions 17a can be accelerated faster than that in an active region 17b by performing the heat treatment after the impurity is introduced in the parts, which are used as the regions 17. Accordingly, the solid phase crystal growth can be generated from the regions 17a toward the region 17b using the nuclei for the crystal growth generated in the regions 17a as seeds. Thereby, the region 17b having a uniform particle diameter is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor in which an active layer is formed by causing solid phase crystal growth in an amorphous semiconductor film.

[Summary of the invention]

The present invention provides a method for manufacturing a thin film transistor as described above, in which device characteristics are improved by introducing impurities into portions of an amorphous semiconductor film that are to be source/drain regions and then causing solid phase crystal growth. This makes it possible to manufacture uniform thin film transistors in a short time.

[Conventional technology]

Thin film transistors are seen as promising as load elements for highly integrated SRAMs and the like. To manufacture this thin film transistor, first an active layer is formed by causing solid-phase crystal growth in an amorphous semiconductor film, and then solid-phase diffusion is performed in the portions of this active layer that are to be source and drain regions. It is common to introduce impurities by ion implantation or ion implantation (for example, Japanese Patent Laid-Open No. 127118/1983).

[Problem to be solved by the invention]

However, in the conventional method as described above, generation of nuclei and growth of crystal grains during solid-phase crystal growth for forming the active layer are slow, so that these generation and growth are performed randomly. This causes variations in grain size in the active region, that is, in the region where the channel is formed. Furthermore, control of particle size is becoming more difficult as channels become shorter.

When the particle size of the active region varies in this way, the device characteristics of the thin film transistor such as leakage current, swing, and mobility also vary.

In addition, in the conventional method described above, solid phase crystal growth is performed to form the active layer, and solid phase crystal growth is performed again on the active layer that has been made amorphous by solid phase diffusion of impurities or impurity ion implantation. Two heat treatments are required to cause this.

Furthermore, since active layers are becoming thinner in order to reduce leakage current, a heat treatment time of about 20 hours is required for solid phase crystal growth. Therefore, thin film transistors cannot be manufactured in a short time.

[Means to solve the problem]

The method for manufacturing a thin film transistor according to the present invention includes introducing impurities into a portion of the amorphous semiconductor film 14 that is to be the source/drain 17a region, and causing solid phase crystal growth in the amorphous semiconductor film 14. It looks like it's going to be heat treated.

[Effect]

In the method for manufacturing a thin film transistor according to the present invention, heat treatment is performed after introducing impurities into the portions to be formed as the source/drain regions 17a.
Solid phase crystal growth in 7a can be made faster than in active region 17b.

Therefore, by using the crystal growth nuclei generated in the source/drain nodding region 17a as seeds and causing solid phase crystal growth from the source/drain region 17a toward the active region 17b, the active region 17b has a uniform grain size. can be formed.

〔Example〕

The first and second embodiments of the present invention will be described below with reference to FIG. This will be explained with reference to FIG.

FIG. 1 shows a first embodiment applied to the manufacture of a so-called top-gate type p-channel thin film transistor.

In this first embodiment, as shown in FIG.
and a polycrystalline Si film 13 having a thickness of about 400 layers are sequentially formed. Then, Si” is applied to the polycrystalline St film 13 by I
This polycrystalline Si film 13 is transformed into an amorphous Si film 14 by ion implantation at a dose of about 0 cm-.

Next, as shown in FIG. 1B, the amorphous Si film 14 is patterned into an island shape, and the Si
NG film 15 and polycrystalline Si film 16 for gate electrode are formed in sequence, and these polycrystalline Si film 16 and SiO2 film 15 are
and is patterned into a gate electrode pattern.

Then, in this state, set B゛ or BF2'' to 5 x IQIS.
By implanting ions at a dose of about c, -2, these ions are introduced into the portions of the amorphous Si film 14 that are to be made into source/drain regions and into the polycrystalline silicon 6.

Next, heat treatment is performed at a temperature of about 600° C. for about 10 hours. FIG. 3 shows the speed of solid phase crystal growth of an amorphous Si film as a change in ultraviolet reflectance.

As is clear from FIG. 3, compared to an amorphous Si film into which only St" is ion-implanted, in an amorphous Si film into which St" and B" are ion-implanted, the number of nuclei for crystal growth is Both generation and grain growth are rapid.

Therefore, the heat treatment time for solid phase crystal growth is approximately 15 hours or more, usually about 20 hours, in the former case, but about 5 hours is sufficient in the latter case. In addition, in order to speed up the solid phase crystal growth in this way, B+ is
It is sufficient to introduce more than about cm-''.

Therefore, by the above-mentioned heat treatment for about 10 hours, solid-phase crystal growth occurs in the portions of the amorphous Si film 14 that should become the source/drain regions, and at the same time, the active regions where crystal growth nuclei have not yet occurred. Crystal grains grow from the ends of the portions that are to become source/drain regions.

? As a result, as shown in FIG. IC, the amorphous Si film 14 becomes a polycrystalline Si film 17 to complete the source/drain regions 17a and the active region 17b, and the active region 17b also has a uniform grain size. are doing. In addition, by the above-mentioned heat treatment,
Solid phase crystal growth also occurs in the polycrystalline Si film 16.

After that, high temperature using halogen lamp or arc lamp, etc.
By applying short-time annealing, polycrystalline Silil
7. Improving the crystallinity of l6 and activating impurities.

FIG. 2 shows a second embodiment applied to the manufacture of a so-called bottom gate type p-channel thin film transistor.

In this second embodiment, as shown in FIG. 2A, a polycrystalline Si film 16 for the gate electrode containing impurities is replaced with SiO2.
Patterning is performed on the film 12, and in this state, a Sing film 15 for a gate insulating film and a polycrystalline Si film 13 are sequentially formed. Then, by ion-implanting Si'' into the polycrystalline Si film 13, the polycrystalline Si film 13 is made into an amorphous Si film 14.

Next, as shown in FIG. 2B, the amorphous Si film 14 and the
．． The film 15 is patterned into an island shape, and the amorphous S
A portion of the i-film 14 that is to be an active region is covered with a photoresist 18.

In this state, B' or BF. ” by ion-implanting the source and the amorphous Si film 14.
These ions are introduced into the area that should be the drain area.

Next, by performing heat treatment at a temperature of about 600° C. for about 10 hours, the amorphous Si film 14 is turned into a polycrystalline Si film 17, as shown in FIG. 2C, in the same manner as in the first embodiment.

Thereafter, high-temperature, short-time annealing using an excimer laser or the like is performed to improve the crystallinity of the polycrystalline Si films 17 and 16 and to activate impurities. Note that this high-temperature, short-time annealing may be performed using a halogen lamp, an arc lamp, or the like, as in the first embodiment.

In the P-channel thin film transistors manufactured in the first and second embodiments as described above, the active region 17b also has a uniform grain size, so device characteristics such as leakage current, swing, and mobility are highly uniform. .

Therefore, SRAMs using these p-channel thin film transistors as load elements have a high manufacturing yield.

〔Effect of the invention〕

In the method for manufacturing a thin film transistor according to the present invention, an active region having a uniform grain size can be formed, so a thin film transistor with uniform device characteristics such as leakage current can be manufactured.

In addition, the solid phase crystal growth of the amorphous semiconductor film itself and the solid phase crystal growth of the source/drain regions are performed in one step, and since this solid phase crystal growth is fast, thin film transistors can be manufactured in a short time. I can do it.

[Brief Description of the Drawings] Figures 1 and 2 are side cross-sectional views sequentially showing the first and second embodiments of the present invention, respectively, and Figure 3 is a graph showing the speed of solid phase crystal growth. . In addition, in the symbols used in the drawings, 171--------...--1...--1 Amorphous S
i film 17a--------source/drain region 1
7b.-1--1 to .--111 active region.

Claims (1)

[Claims] Manufacture of a thin film transistor by introducing impurities into portions of an amorphous semiconductor film that are to be source/drain regions, and performing heat treatment to cause solid phase crystal growth in the amorphous semiconductor film. Method.