JPH03216036A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To apply synchronization processing in time division by a single circuit and to make the circuit small and to reduce the cost by using a counter circuit, a shift circuit and a storage circuit. CONSTITUTION:A multi-frame signal being an input signal 10 is given to a shift circuit 1, in which the signal is subject to time division sequentially, and a resulting parallel data 20 for each multi-frame is stored in a memory circuit 2. A counter circuit 3 counts number of pulses of the multi-frame of the input signal and outputs a count 40. A discrimination circuit 4 receives the count 40 and the parallel data 20 to output a synchronization timing output 60 of multi-frame. Then the memory circuit 2 receives the parallel signal 20 of the shift circuit 1 and the count 40 of the counter circuit 3 and outputs a synchronizing data signal 30. Thus, the circuit is made small and the cost is reduced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a multi-frame signal synchronization circuit for data communication equipment, and particularly to a synchronization circuit for multi-frame signals in data communication equipment, and in particular, when outputting a parallel signal from one serial signal input, it is possible to synchronize many multi-frame signals. This invention relates to a synchronization circuit when synchronization must be performed serially.

[Conventional technology]

Conventionally, this type of synchronous circuit converts N multi-frame data signals of a serial input signal 10 into parallel data signals by a serial-parallel converter 100, as shown in FIG. Ion
After the synchronization is detected by the synchronization determination circuit 200, the parallel-to-serial conversion circuit 300 converts the signals to obtain a synchronization data output 30 and a synchronization timing output 60. [Problems to be Solved by the Invention] The conventional synchronization circuit described above decomposes input data into individual parallel signals and uses one circuit for each for synchronization, so the amount of data in the multi-frame signal is enormous. This has the disadvantage that the number of synchronization determination circuits increases, which becomes an obstacle to miniaturization and cost reduction of the device.

[Means to solve the problem]

The synchronous circuit of the present invention includes a counter circuit that counts serial multi-frame signals input to a data communication device and outputs a counter value, and a synchronous data signal of multi-frames from the serial multi-frame signal and a memory circuit to be described later. a shift circuit that inputs and shifts the signal and outputs a parallel signal, and a memory that inputs the parallel signal of the shift circuit and the counter value of the counter circuit and outputs a synchronous data signal and a counter clear signal to the counter circuit. and a determination circuit that inputs the counter value and the parallel signal of the shift circuit to determine synchronization timing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. A multi-frame signal as an input signal is sequentially time-divided by a shift circuit 1, and parallel data 20 is stored in a memory circuit 2 for each multi-frame. On the other hand, the counter circuit 3 counts the number of multi-frame pulses of the input signal and outputs a counter value 40. The determination circuit 4 inputs this counter value 40 and the parallel data 20 and outputs a multi-frame synchronization timing output 60. When the synchronization pattern of the judgment circuit 4 is rectified, the judgment circuit 4 sends a signal to the counter circuit 3.
Counter clear output 70 sets the counter value to initial value 1
is output. The count value 40 is also input to the memory circuit 2, and the counter value 50 output at the next memory output timing is counted up by the counter circuit 3, and the multi-frame timing is captured each time. In this way, the synchronous circuit can be realized with a simple circuit configuration using a shift circuit, a memory circuit, and a counter circuit, and these circuits can also be easily realized as an LSI.

〔Effect of the invention〕

As explained above, by using a counter circuit, a shift circuit, and a memory circuit, the present invention can provide a synchronization circuit that performs synchronization processing in a time-division manner in a single circuit, thereby reducing the circuit size, miniaturization, and cost. effective. Furthermore, since the circuit is suitable for small-sized LSI even when dealing with a huge amount of data, it is possible to further increase the effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a synchronous circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional synchronous circuit. DESCRIPTION OF SYMBOLS 1... Shift circuit, 2... Memory circuit, 3... Counter circuit, 4... Judgment circuit, 10... Input signal,
20... Parallel data, 30... Synchronous data output, 40, 50... Counter value, 60... Synchronous timing output, 70... Counter clear output, 100...
- Serial/parallel conversion circuit, 200... Synchronization determination circuit, 300... Parallel/serial conversion circuit.

Claims (1)

[Scope of Claims] 1. A counter circuit that counts serial multi-frame signals input to a data communication device and outputs a counter value, and synchronized multi-frame data from the serial multi-frame signal and a memory circuit to be described later. a shift circuit that inputs and shifts a signal and outputs a parallel signal; and a shift circuit that inputs the parallel signal of the shift circuit and the counter value of the counter circuit and outputs a synchronous data signal and a counter clear signal to the counter circuit. 1. A synchronization circuit comprising: a memory circuit for determining synchronization timing; and a determination circuit for determining synchronization timing by inputting the counter value and a parallel signal from the shift circuit. 2. The synchronous circuit according to claim 1, wherein the counter circuit, shift circuit, and memory circuit are formed of LSI circuits.