JPH04104628A - Multi-frame pattern detection system - Google Patents

Abstract

PURPOSE:To detect a head of a multi-frame in a short time and to take synchronization of a reception data by detecting a change bit of a data entering a hunting object period and comparing the bit with a bit pattern so as to detect the synchronization. CONSTITUTION:A counter 31 and a NOT gate 33 generate a clock HTG taking a prescribed period such as 20.8mus as a hunting object period from the start of the reception mode. Then an AND gate 32 ANDing the clock HTG and a reception data XRD is provided to input bits of the reception data XRD within a prescribed period (20.8mus) from the start of the reception mode to a next stage synchronization pattern detection circuit 34 as they are, and other data are inputted in 0 pattern entirely. Thus, the object bits of the hunting in the synchronization pattern of the reception data are limited. Thus, a chance of hunting the frame from the head is increased and the time when the head of the multi-frame is detected is decreased to quicken the synchronization probability.

Description

[Detailed Description of the Invention] [Summary] Multi-frame pattern detection that achieves synchronization by detecting a multi-frame pattern indicating the beginning of a multi-frame from a bit sequence of received data in a synchronization circuit of a transmitting/receiving device that performs time-division transmission. The purpose of this method is to synchronize received data by making it possible to detect the beginning of a multi-frame in a short time. The data frame having a multi-frame bit M indicating the start of the frame at the beginning is transmitted by a time division transmission method that switches between transmission and reception modes, and the frame bit F and the multi-frame located at the beginning of the data frame in the reception mode are transmitted. In a synchronization circuit that detects synchronization of transmission data by extracting a bit corresponding to the bit pattern of bit M, the time t from the start of reception mode during which the bit pattern of the data frame with the maximum delay that is taken in as valid can be extracted. The bit hunting target section is set as a bit hunting target section, and synchronization is detected by detecting a changed bit of the data that falls within the hunting target section and comparing it with the bit pattern.

[Industrial application field]

The present invention relates to a multiframe pattern detection method for synchronizing a transmitting/receiving device that performs time-division transmission by detecting a multiframe pattern indicating the beginning of a multiframe from a bit sequence of received data.

One of the digital subscriber line transmission systems is the time division transmission system (
There is a so-called Bing Bong transmission method), in which transmission and reception times are divided and transmission is performed alternately. In a transmitting/receiving device that performs ping-pong transmission, the transmission time and reception time are divided at regular intervals. Furthermore, since the transmission band of audio signals is limited to 0.3 to 3°4 kHz, according to the sampling theorem, the original signal can be reproduced by sampling at 6 or 8 kHz or higher, so in reality, the band limit is not met. Taking into consideration the characteristics of the filter used, 8 kHz is used as the sampling frequency. In terms of time, the sampling interval is 125 μs. In other words, if an 8-bit encoded digital signal can be transmitted once every 125 μs, the voice quality can be maintained. Therefore, the transmission/reception switching cycle may be 125 μs if the signal is an audio signal.

On the station side, first, the pulse train to be transmitted to the terminal side is converted into a burst-like pulse train at approximately twice the speed, and then sent to the subscriber line. When the terminal side receives this pulse train, there is still about half the time left, so it uses this free time to send out a burst-like pulse train in the opposite direction, that is, from the terminal side to the station side, to the subscriber line. When the station side receives this, it sends out the next burst-shaped pulse train using the same operation again, and so on, the transmission bursts from the station side and the terminal side are sent to each other alternately in a time-sharing manner over a pair of metallic cables. It is something.

In addition, in communication networks constructed with a large number of subscribers, such as ISDN, data from each subscriber is predetermined in order to make effective use of each subscriber's data. The images are transmitted sequentially in order and with the multi-frame pattern focus set to j]0. In a device that receives the data, it is desired to detect frames in a short time because the device detects a multi-frame pattern as a criterion for determining whether the received data is valid or invalid.

[Conventional technology]

FIG. 6 shows the format of the communication data to be transmitted. Figure 6(a) is a frame configuration diagram, Figure 6(b) is each bit pattern of frame and multi-frame, Figure 6(C) is
shows a multi-frame configuration diagram. In FIG. 6(a), the data format of one frame includes a frame bit F indicating the beginning of each frame, a multiframe bit M indicating the beginning of a multiframe consisting of 16 frames, and bO in which data of the Bl channel is carried. ~8 up to b7
Bit, B2 channel data is carried.

It consists of 20 bits: 8 pins from 1 to b7, a control bit D carrying control data, and a balance bit b.

The relationship between frame bits F and multiframe bits M is determined as shown in the bit pattern shown in FIG. 6(b). That is, the first frame TO (the first frame of the multi-frame) is assigned the combination rlo of frame bit F and multi-frame bit M, and by detecting this 10J bit pattern, the multi-frame The first frame can be detected.

Then, in the second frame T1, the frame bit F
and a combination of multi-frame bits M roIJ, the third frame T2 is assigned a combination rl tJ of frame bits F and multi-frame bits M, and after that, odd numbers 7Lz-muharo IJ,
Even number 7 C4 H Ir11 J is assigned. .

A random pattern of encoded data is carried on the 8 bits from bo to bit b7, where data of the B1 channel is carried.B2 channel data is carried.bo to bit b7.

Control data C shown in FIG. 6(C) is stored in the control bin L-D.
O to C15 are included. Note that 8 bits from CO to C7 represent one control signal, and 8 bits from 08 to C150 represent one control B signal.

FIG. 7 shows a processing flow of conventional multi-frame pattern detection. Conventional multi-pattern detection starts with a one-bit shift (step 70) from the reception mode start point.
0) and hunts for "10A" indicating the beginning of the multiframe (step 701). Note that from the start of the reception mode to the received data is all O's. rl
If the oJ pattern has been detected (YES in step 701), initial value setting M=0 is performed (step 702).
Next, a pattern at the same time position of the received frame is detected, and it is determined whether it is an r011 pattern (step 7
03). Here, if the pattern is roIJ (YES in step 703), count up M by 1 (step 704) and check whether the next pattern is "11" at the same time position of the next received frame. A determination is made (step 706). Thereafter, if the bit pattern condition is satisfied at the same time position, the process goes through steps 703 to 707 consisting of repeating ro IJ and '11J, and if the condition of M=15 in step 705 is satisfied (step 70
5: YES), remove this loop. Then, if there is rlOJ at the same time position (Y in step 708),
ES), synchronization is established (step 709). but,
If the bit pattern condition is not satisfied at the same time position (No in steps 703, 706, and 708), shift by 1 bit (step 700), and detect rl OJ indicating the beginning of the multiframe again (step 701).
).

FIG. 8 shows a conventional focus hunting procedure.

Since the receiving device may be plugged into an outlet or the like during the process, it does not necessarily start hunting from the start of the receiving mode. Now, when we start hunting for 1r10J from frame T2, all bits in the non-receiving period before data reception are O, so we start hunting for the first "'10 (■')" of the 4.5th bit of the received data. death,
Estimated to be the beginning of the multi-frame. The same time positions (4th and 5th bits) of the received data received from this point on are shown in Figure 6 (
If the bit pattern condition shown in b) is satisfied, it is considered to be the beginning of a multiframe.

However, in this example, the next received data (frame T
The 4.5th bit of 3) is “10 (■’)”, and the 6th bit is
Since the bit pattern ("01") shown in Figure (b) is not satisfied, the 6.7th bit "10" is hunted while shifting one pin at a time.Then, the next received data ( It is determined whether the same time position (6th and 7th bits) of frame T4) satisfies the bit pattern shown in FIG. 6(b).

In this example shown in FIG. 8, if the bit pattern conditions in FIG. 6(b) are no longer satisfied (■, ■', ■',
[Phase]', @'), shift the focus one by one, and then hunt for the next 10 points (■', ■', ■'
,■′).

Last 20th focus of received data (frame T8 in the figure)
When the beginning of the multi-frame cannot be found at this point, the search is performed again from the start of the reception mode for the next reception data (frame T9) (0' to Φ').

If the above procedure is repeated and hunting is started from the beginning of frame To, synchronization can be achieved because the relative hit-and-turn condition shown in FIG. 6(b) is satisfied.

[Problems to be Solved by the Invention] In the conventional 1-bit/7-bit shift hunting method shown in FIG. 8, synchronization detection starts at the beginning of the frame when the terminal is turned on halfway, etc. Frame TO
For example, as shown in FIG. 8, synchronization detection may start from the 4.5th bit rlol of frame T2. In this way, when information bits that originally occur randomly become a fixed pattern, synchronization cannot be achieved and the hunting operation becomes a loop.

An object of the present invention is to synchronize received data by making it possible to detect the beginning of a multiframe in a short time.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. In the figure, the upper row shows a timing chart for switching between transmission and reception modes in ping-pong transmission, and the lower row shows the reception time status of received data. The received data has a frame bit F indicating the start of a data frame at the beginning, and a multiframe bit M indicating the start of a multiframe composed of a plurality of data frames. By extracting bits corresponding to the bit patterns of frame bits F and multiframe bits M of this received data, synchronization of transmission data is detected.

Then, the period from the start of the data reception period to the time t when the bit pattern of the data with the maximum delay can be extracted from the data effectively captured within the reception period is set as the hunting target period, and change bits in the received data that fall within the hunting period are detected. and detects synchronization by comparing it with the bit pattern.

[For production]

In the present invention, the period from the start of reception of transmission data to the bit pattern detection time t of the received data with the maximum delay is targeted for hunting. Therefore, the bits of the received data that fall within this hunting target section become the hunting target, and when the hunting target interval is exceeded, the process returns to the reception start point and starts bit pattern hunting from the beginning of the data frame.

〔Example〕

FIG. 2 is a diagram showing extracted bit sections of received data according to the present invention. In the figure, signal 5R3L is a clock that separates the reception/transmission mode of the device, and signal HTG is “1”.
'' is a signal indicating that it is a hunting target section. For example, in 384 kb/s transmission, when transmitting and receiving modes are repeated at 125 μs, a capacity of 48 bits per 125 μs is set. Considering that the reception mode usually has a delay depending on the distance, the time is slightly longer than the transmission mode. In this example, the time allocation for the transmission mode is 57.3 μs for 22 bits, and the time for the reception mode. The allocation is 67.7 μs for 26 bits.

Since the signal cannot be regenerated accurately unless the received data is captured within the receive mode time, 1
The received data XRD received within 5.6 μs is valid. The hunting target section is set to 20.8 μs from the start of the reception mode so that the frame bit F and multi-frame bit M of the received data (2) with the maximum delay of valid received data can be seen. Therefore, the received data
If it is 1, the 1st to 6th bits of the received data are the hunting target section, and if the received data XRD2 is delayed by about 10 μs from the reception mode start time,
The first to third bits of the received data are the hunting target section.

FIG. 3 is a block diagram of a multi-frame pattern detection circuit according to the present invention. In the figure, reception/transmission mode switching signal 5
Counter 31 whose main power is RSL and extraction cooler RcK
starts counting with the clock RCK from the time when 5R3L changes to -rOJ (at the start of the reception mode), and keeps the output signal HTG at rlj until it counts 8. These 8 counts (one count is 2.6 μs) are 20.8 μs in which the multi-frame bit M and frame bit F of the received data XRD with the maximum delay can be used as a hunting period. f14 of output signal HTG
enters the AND gate 32, so the received data XRD is selected and input to the synchronization pattern detection circuit 34. On the other hand, when 5R3L changes to the transmission mode (ro" → flj), the counter 3 is reset by the reset signal from the not gate 33.
1 is reset, and the output signal HTG of the counter 31 becomes "
0". Therefore, the output of the received data XRD is stopped by the AND gate 32.

That is, the counter 31 and the not gate 33 create a clock HTG (see FIG. 2) whose hunting target period is a certain period (for example, 20.8 μs) from the start of the reception mode. Then, this clock HT (, and the received data
By providing an AND gate 32 that takes an AND with RD, a certain period of time (in the above example, 20
．． The bits of the received data be done. The synchronization pattern detection circuit 34 extracts the received data
This is to determine whether a bit pattern condition other than 001 is satisfied.

When the synchronization pattern detection circuit 34 detects a pattern other than roOJ, it sets “0” to the frame counter 35 at the next stage.
Sends a load signal. If the pattern condition is no longer satisfied midway through, the frame counter 35 sends a "0 load signal" starting from the count value. When the frame counter 35 counts a predetermined number, it transmits the FM pattern detection timing signal to the multi-frame frame counter 35. The multi-frame synchronization circuit 36 receives this timing signal and sends it to the synchronization circuit 36.
j detection and the counter load pulse are logically summed by the OR gate 27, the multi-frame counter starts operating, and synchronization establishment is recognized by counting 16 frames, and the start point of the frame is determined at this timing. It becomes possible to separate each channel and capture the received data.

FIG. 4 shows a processing flow for multi-frame pattern detection according to the present invention. In the figure, by masking the hunting target bit pattern of the received data XRD with HTG, the information bits of the received data XRD outside the hunting section become an O pattern. Therefore, in the present invention, fo
Since patterns other than offl appear only in the hunting target section, hunting for the frame pattern of the next frame is limited to the bits in the hunting target interval. The processing flow will be explained below.

When synchronization establishment starts, while performing a 1-bit shift operation (step 400), I'
Hunting other than OOJ (No in step 405)
). At this time, (i)? If you hunt Oit (step 411)
(Yes), the same time position of the next received frame is r
ll'' (Yes at step 412), the same time position of the next received frame is hunted again, and! When r10, , (Ye in step 413)
s) Proceed to step 403 and detect a multi-frame pattern using the same processing flow as before (step 403
~41O), other than f 11 J, Y 102 (
D Tokiniha (NO in step 413), step 400
Return to

(ii) When hunting '114 (Stets 7")
If the same time position of the next received frame is Ir01j (No in step 411), the same time position of the next received frame is hunted again, and if it is other than FO1j (in step 414 No
) Return to step 4.00.

(iii) When hunting rloj (ste.

Step 402: Yes), the multi-frame pattern is detected using the same processing flow as before (Steps 403 to 41).
0).

If you pass through the hunting target section, everything will be "00"
Therefore, hunting will be performed again from the receiving mote starting position.

FIG. 5 is a diagram showing a hunting procedure according to the present invention. In this example, the received data is received with a delay of 5.2 μs from the start of the reception mode due to delays such as transmission distance. For example, when synchronization detection starts from frame T2, "01 (■)" including the first 1st bit is hunted. Then, it is determined whether the same time position of received data XRD received from now on satisfies the bit pattern condition shown in FIG. 6(b).

However, in this example, the bit position of the next received data XRD (frame T3) is "00 (■)",
Since it does not satisfy the focus pattern ("10" or "11") shown in FIG. 6(b), it is shifted by 1 bit and r
Look for patterns other than "oo". “Ol” (■) is found in the 1st and 2nd bits of the hunting target section, and 1 and 2 of the next received data XRD (frame T4) are found.
Find "11(■)°" for the th bit. In the same way, check whether the bit pattern of the 12th bit of the next received data (frame T5) satisfies the condition shown in FIG. 6(b).
I approve.

In this example, since the bit pattern "r10" at the beginning of the multi-frame is detected at {circle around (2)}, the multi-pattern can be detected and synchronization can be established by hunting [phase] to {circle over (2)}.

In this way, in the present invention, the hunting target interval is set to 20.8 μs from the reception mode, and hunting is performed for 1 bit to 6 bits of received data that falls within this range, and 1 bit before and after that, so even if the hunting target interval is 20.8 μs from the reception mode, Even if synchronization starts from the frame of , if it is outside the hunting target section, it will be a 00j pattern, so it will only perform a bit shift operation and will not extract bits between frames. By using a method of hunting patterns and establishing synchronization by setting 0 patterns consecutively in areas other than the target section, the opportunity to hunt the beginning of the frame TO increases compared to the conventional method, and the time required to establish synchronization is shortened. .

〔Effect of the invention〕

As explained above, in the present invention, since the hunting target section of the received data to the synchronization circuit is limited to a certain period of time from the start of the reception state,
There will be more opportunities to hunt ゛. Therefore, there is an increased chance of hunting the frame TO from the beginning, and the time for detecting the beginning of a multiframe is shortened, making it possible to speed up the establishment of synchronization.

Furthermore, even if synchronization establishment is started from the middle of the frame, if it is outside the hunting target section, it will not be focused on for synchronization establishment, thereby eliminating unnecessary processing.

FIG. 5 shows the processing flow of the present invention, FIG. 6 shows the transmitted data format, and FIG. 7 shows the conventional multi-frame pattern detection processing flow. FIG. 8 shows the hunting procedure.

Agent Patent Attorney Sada Igeta-'・,・♀・',;-$f
;

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a diagram showing an extracted bit section of received data according to the present invention. FIG. 3 is a block diagram of a multi-frame pattern detection circuit according to the present invention. Detection of multi-frame patterns of b) Frame 771, 1,000 7, 7 -to -7, 7th Buddha Extension 6 Tuff Suma, 7 -to -began Figure Figure Figure Figure 0IOCIIIQIIO! Juzo no Hi, 71-
Hunchin 7゛°now 111ip.

Claims (1)

[Claims] 1. Transmitting/receiving the data frame having at the beginning a frame bit F indicating the start of the data frame and a multi-frame bit M indicating the start of a multi-frame composed of a plurality of the data frames. The synchronization of the transmitted data is detected by transmitting using a time-division transmission method that switches modes, and extracting bits corresponding to the bit pattern of the frame bit F and multi-frame bit M located at the beginning of the data frame in the reception mode. In the synchronous circuit, a period from the start of reception mode to a time t when the bit pattern of the data frame with the maximum delay that is taken in as valid can be extracted is set as a bit hunting target section, and changing bits are detected and compared with the bit pattern. A multi-frame pattern detection method characterized by detecting synchronization.