JPH0522421B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a terminal device that is housed in an automatic exchange via a two-wire line using an up and down time division transmission system (so-called ping-pong transmission system). In particular, the present invention relates to a synchronization detection circuit that shortens the time required to establish synchronization at the start of communication.

(b) Background of the Technology Attempts have been made to accommodate not only telephone terminal devices in automatic exchanges, but also non-telephone terminal devices that provide services such as data communications.

In order to accommodate such a terminal device in an automatic exchange via a two-wire line, the two-wire line is connected at a predetermined period (for example, 8 A synchronization code F for recognizing the start of a signal in each transmission period, a control channel D for transmitting a control signal, and An up and down time division transmission system (so-called ping-pong transmission system) is used in which mutual communication is performed by transmitting burst signals made up of data channels B1 to Bi that transmit voice/data.

When communicating using this type of uplink/downlink time-division transmission method, the receiving device detects the synchronization code F that the transmitting device sends at the beginning of the transmission period, and switches transmission and reception between the automatic exchange and the terminal device. It is necessary to match the timing (confirm synchronization).

(c) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional synchronization detection circuit in this type of terminal device.

In FIG. 1, during the reception period of the terminal device,
A reception signal transmitted via a two-wire line 1 from an automatic exchange (not shown) is received by a reception circuit 3 via a two-wire/four-wire conversion circuit 2, and is transmitted to a separation circuit 4.

The separation circuit 4 learns the start of the received signal from the transmission/reception switching signal e outputted from the transmission/reception switching counting circuit 9, counts a predetermined number of clock signals (not shown, the same applies hereinafter) synchronized with the received signal, and calculates the clock signal e. By extracting the same number of bit signals as the number, the part corresponding to the reception synchronization code F is separated from the reception signal transmitted from the reception circuit 3, and the rest is set as fixed data (for example, all "0"). is transmitted to the synchronization code recognition circuit 5 as the synchronization code signal rc.

The synchronization code recognition circuit 5 compares the separated received synchronization code F portion with a predetermined synchronization pattern, and if they match, outputs a detection signal d.

On the other hand, when the terminal device is transmitting, the synthesis circuit 6 uses the transmission synchronization code F transmitted from the synchronization code generation circuit 7.
The signal sc is combined with the transmission data sd to create a transmission signal, which is transmitted to the transmission circuit 8. The transmitting circuit 8 sends the transmitted signal to the two-wire line 1 via the two-wire/four-wire conversion circuit 2.

The transmission timing and reception timing of the terminal device are identified by the transmission/reception switching signal e sent out by the transmission/reception switching counting circuit 9. The transmission/reception switching counting circuit 9 calculates the transmission period and reception by counting a predetermined number of clock signals synchronized with the received signal based on the detection signal d outputted when the synchronization code recognition circuit 5 detects the reception synchronization code F. A period is determined, and a transmission/reception switching signal e with a logic value of '1' is output during the transmission period, and a transmission/reception switching signal e with a logic value of '0' is output during the reception period.

As a result, the combining circuit 6 and the transmitting circuit 8 are activated during the transmitting period, and the receiving circuit 3 and the separating circuit 4 are activated during the receiving period.

FIG. 5 is a diagram showing a conventional synchronization establishment sequence, and FIG. 6 is a diagram showing a conventional operation sequence during synchronization code detection.

As shown in FIG. 5, at the beginning of communication, the terminal device and the automatic exchange each set their own transmission period and reception period, and the automatic exchange uses the control channel D and data channel of the transmission signal during the transmission period. B1 to Bi are set to a fixed pattern (for example, all '0') and transmitted, and the terminal device attempts to detect the reception synchronization code F from the automatic exchange during the reception period.

The conventional detection operation of the reception synchronization code F will be explained in more detail with reference to FIG.

As shown in FIG. 6, the separation circuit 4 first separates the bits between the start timing t1 of the reception period and a predetermined number of clocks as the synchronization code F, and uses the rest as fixed data (all bits). 0') is sent to the synchronization code recognition circuit 5 as the received synchronization code F signal rc as described above, and in the synchronization code recognition circuit 5, the received synchronization code F signal rc is predetermined as described above. Compare with sync pattern.

At this time, the automatic switchboard and terminal equipment are still
The signal transmission/reception switching timing is not correct. Therefore, the synchronization code recognition circuit 5 cannot find the received synchronization code F and does not output the detection signal d.

Therefore, if the detection signal d is not output during the certain period (at least one transmission/reception cycle), the transmission/reception switching counting circuit 9 determines that the transmission/reception switching timing is not correct, and in the next cycle, the above-set One transmission/reception period of the transmission period and reception period is displaced (shifted) by one clock in a certain direction. (6th
(The figure shows an example in which the signal is shifted to the left.) In other words, as described above, if the signal transmission/reception switching timing is not yet synchronized between the automatic exchange and the terminal device, the reception synchronization code F In the signal rc, the transmission signal from the automatic exchange and the transmission signal from the terminal device overlap, and it cannot be predicted that the reception synchronization code F to be detected will always be detected within, for example, one transmission/reception cycle.

Therefore, first, the detection timing of the reception synchronization code F is fixed to a period corresponding to the reception synchronization code F from the start timing t1 of the reception period of the transmission/reception switching signal e generated by the terminal device.

However, if we always look at the same period, we will be unable to detect the reception synchronization code F forever, so we
The timing of displacement (shift) (in Figure 6,
As mentioned above, the bits between a predetermined number of clocks from a shift to the left (that is, a timing advanced by one clock) are regarded as a synchronization code F, and the separated bits are compared with a predetermined synchronization pattern. By repeating this, the reception synchronization code F can be detected at least until the number of displacements (shifts) becomes equal to the number of clocks in one transmission/reception cycle.

This reception synchronization code F detection method is, for example, a technique similar to a well-known "frame synchronization method" in the field of transmission technology.

Therefore, in the conventional system, detection of the next reception synchronization code F cannot be attempted until after at least one transmission/reception synchronization.

The above process is repeated until the detection signal d is output. When the synchronization code recognition circuit 5 successfully detects the reception synchronization signal F and outputs the detection signal d, the transmission/reception switching counting circuit 9 stops the displacement (shift) operation and , maintains the switching timing of the transmission period and reception period,
The coincidence circuit 12 starts counting the detection signal d, and when the synchronization code F is detected m times (m is an integer greater than or equal to '1') consecutively, synchronization from the automatic exchange to the terminal device is established. do. (See Figure 5) On the other hand, unlike the terminal equipment, the automatic exchange side does not change the switching timing of the transmission/reception switching signal, but waits for the synchronization code F from the terminal equipment to be detected during the initially determined reception period. There is. If the terminal equipment side shifts the transmission/reception switching timing, detects the synchronization code F from the automatic exchange side, and maintains the transmission/reception switching timing, the automatic exchange side will inevitably be able to detect the synchronization code F from the terminal transmission/reception. When the synchronization code F is detected l times (l is an integer greater than or equal to '1', l>m) consecutively, synchronization is established, and it becomes significant for the control channel D of the transmission signal and the data channels B1 to B1. Communication is started by transmitting the necessary data to the terminal device. (See Figure 5) As is clear from the above explanation, in the conventional synchronization detection circuit, when starting communication, the terminal device sets the transmission period and reception period independently of the automatic exchange, and While displacing (shifting) the reception period by one clock for each transmission/reception period,
During the reception period, an attempt is made to detect the reception synchronization code F from the automatic exchange. Therefore, the number of shifts (shifts) times one transmission/reception cycle is required until the counting of the detection of the synchronization code F (counting of m and l above) is started to establish synchronization between the automatic exchange and the terminal equipment. The drawback was that it took a long time.

(d) Object of the Invention An object of the present invention is to eliminate the drawbacks of the conventional synchronization detection circuit as described above, and to realize a means for shortening the synchronization determination time at the start of communication as much as possible.

(e) Structure of the Invention The object of the present invention is to detect a synchronization code from a transmission signal transmitted from the automatic exchange in a terminal device accommodated in an automatic exchange via a two-wire line using an uplink and downlink time division transmission system. a synchronization code detection means for detecting and outputting a detection signal, and shifting the extraction timing from the received signal by one clock until receiving the detection signal and outputting it to the synchronization code detection means;
After receiving the detection signal, separating means separates the synchronization code from the reception signal at an extraction timing determined based on the detection signal and outputs it to the synchronization code detection means, and a separation means switches the transmission/reception timing based on the detection signal. This is achieved by providing a transmitting/receiving switching means for performing the transmission and receiving, and a holding means for suppressing the switching to the transmitting state from the transmitting/receiving switching means and holding the terminal device in the receiving state until the detection signal reaches a predetermined number of times. .

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a synchronization detection circuit according to an embodiment of the present invention, FIG. 3 is a diagram showing a synchronization establishment sequence of the present invention, and FIG. 7 is a diagram showing a synchronization code detection circuit of the present invention; , is a diagram showing an operation sequence during continuous detection n times. Note that the same reference numerals indicate the same objects throughout the figures.

First, as shown in FIG. 2, in the present invention, a counting circuit 10 and a gate 11 are newly provided. The gate 11 suppresses transmission data from a terminal device and maintains the terminal device in a receiving state, thereby preventing collision between transmission data and reception data when synchronization is not determined.

The counting circuit 10 is a counting circuit for preventing pseudo synchronization, and outputs a detection signal d when the synchronization code recognition circuit 5' detects the received synchronization code F signal rc.
, and continuously calculate the predetermined standard number n.
(However, when n reaches an integer greater than or equal to '1'), a count output g is outputted, and the gate 11 is made conductive.

In the communication suspension state, the counting circuit 10 is not outputting the counting output g, so the gate 11 is in the blocking state, and the transmission/reception switching signal e output from the transmission/reception switching counting circuit 9 is set to a logical value by the gate 11. '
Maintained at 0'.

As a result, the receiving circuit 3 and the separating circuit 4' are energized, the combining circuit 6 and the transmitting circuit 8 are not energized, and the terminal device enters the receiving state.

The separation circuit 4' is a conventional separation circuit 4 (first
(see figure), the synchronization code F, control channel D, data channel B1 to
When the gate 11 is in a conductive state, the beginning of the received signal is detected by the transmission/reception switching signal e, and when the gate 11 is in the inhibited state, the beginning of the received signal is detected, and a clock signal synchronized with the received signal is detected. a predetermined number of {transmission/reception switching signal e and detection signal d, the seventh
As shown in Figures A and B, the predetermined numbers are different.
By counting the synchronization code F, the extraction timing of the synchronization code F is determined, the synchronization code F part is separated, and the data other than the separated synchronization code F part are fixed data (for example, all '
0') is output to the synchronization code recognition circuit 5' as the synchronization code F signal rc. However, if the transmission/reception switching signal e and the detection signal d are not output for a certain period of time, the received signal is output to the side synchronization code recognition circuit 5'.

Therefore, the synchronization code recognition circuit 5' first receives the synchronization code F signal rc input from the separation circuit 4' while in the reception state (in the reception state, it is the same as the received signal as described above). ) is compared with a predetermined synchronization pattern using a clock synchronized with this while shifting (shifting) one clock at a time, as shown in FIG. 7 (synchronization code comparison).
If they match, a synchronization signal d is output.

The received signal always includes the reception synchronization code F once during one transmission/reception synchronization, and the reception signal is
1, there is no collision with the transmitted data, so that the reception synchronization code F can be detected within one transmission/reception cycle at most, as shown by double hatching in FIG.

In the conventional method, as described above, the reception synchronization code F is detected while shifting the reception period by one clock every one transmission and reception period. shift)
Although it took twice as long as the number of times, as mentioned above,
In the case of the present invention, the reception synchronization code F can always be detected during one transmission/reception period at most.

In the present invention, in this way, the gate 11
Until it is recognized that the synchronization signal F has been properly detected, the transmission signal from the exchange side is received, and the detection timing is shifted one clock at a time, and the reception synchronization code F is detected. It is distinctive in that it attempts to do so.

Each circuit of the synchronization detection circuit of the present invention functions as described above, so when communication is started, the automatic exchange independently sets the transmission period and reception period and sends the During the period, the control channel D and data channels B1 to Bi of the transmission signal are set to a fixed pattern (for example, all '0's) and transmitted.

On the other hand, since the combining circuit 6 and the transmitting circuit 8 are not energized, the terminal device exclusively maintains the receiving state as described above, and the separating circuit 4' receives the transmission/reception switching signal e and the detection signal d. Since there is no input, the received signal transmitted from the receiving circuit 3 is then transmitted to the synchronization code recognition circuit 5'.

Here, the synchronization code recognition circuit 5' displaces (shifts) the synchronization code F signal rc transmitted from the separation circuit 4' by one clock at a time in synchronization with the synchronization code F signal rc, and in advance, An attempt is made to detect the received synchronization code F by comparing it with a predetermined synchronization pattern. At this time, the synchronization code F signal rc is the reception signal itself from the reception circuit 3, and since the reception signal always includes the reception synchronization code F once during one transmission and reception cycle, the maximum number of transmission and reception cycles is one transmission and reception cycle. The received synchronization code F is detected within the period. (Refer to the sequence during synchronization code detection in FIG. 7) In this way, the synchronization code recognition circuit 5'
When the reception synchronization code F is detected, the detection signal d is transmitted to the separation circuit 4' to hold the extraction timing of the reception synchronization code F, and the count signal d is also transmitted to the transmission/reception switching counting circuit 9 and the counting circuit 10. do.

As in FIG. 1, the transmission/reception switching counting circuit 9 determines, holds, and transmits the switching timing of the transmission period and reception period of the transmission/reception switching signal e.
Since the gate 11 is still in the blocking state, the terminal device maintains the receiving state.

In the reception state, the separation circuit 4' receives the detection signal d sent from the synchronization code recognition circuit 5', as described above, until the gate 11 becomes conductive.
The received synchronization code F is separated from the synchronization code F extraction period determined based on
The rest is fixed data and the whole is synchronized code F signal rc
The signal is output to the synchronization code recognition circuit 5' as a signal.

The counting circuit 10 counts the detection signal d transmitted from the synchronization code recognition circuit 5', and when the number of consecutive detections reaches the aforementioned reference number n, it outputs a counting output g and makes the gate 11 conductive. .

As a result, the transmission/reception switching counting circuit 9 counts and generates a predetermined number of clocks from the time when the detection signal d of the synchronization code F is received, and a logical value '1' is generated for each transmission/reception cycle. When the transmission/reception switching signal e switched to '0' is output via the gate 11, the transmission synchronization code F signal sc generated by the synchronization code generation circuit 7 at the beginning of the transmission period (logic '1' period) is transmitted to the transmitting circuit 8 via the combining circuit 6, and sent to the two-wire line 1 via the two-wire/four-wire conversion circuit 2.

Further, at this time, the gate 13 which had been blocking the output of the detection signal d to the synchronous counting circuit 12 also becomes conductive, and the synchronous counting circuit 12 starts counting the detection signal d. The subsequent operations from establishing synchronization to starting communication are the same as in the conventional method.

Figure 7 shows the above operation sequence.
FIG. In the case of the present invention, the terminal device receives the reception signal sent from the automatic exchange in the separation circuit 4' exclusively in the receiving state, and sends the separated synchronization code F to the synchronization code recognition circuit 5'. , when the synchronization code F is compared and a match is detected in the synchronization code recognition circuit 5', the detection signal d is sent to the counting circuit 10, and when the detection signal d is detected n times in succession, the separation circuit 4' At this time, the reception synchronization code F separated at the above timing is recognized as the regular reception synchronization code F, and the gate 11 is turned on (at its timing). At this point, already
The transmission/reception switching signal e at the timing determined and held by the transmission/reception switching counting circuit 9 is sent out, and thereafter,
In the same operation as the conventional method, synchronization is established by detecting the synchronization code F m and l times in the synchronization counting circuit 12 of the terminal device and the automatic exchange.

As is clear from the above description, according to this embodiment, at the beginning of communication, the terminal device exclusively maintains the reception state and detects the reception synchronization code F while shifting the reception signal one clock at a time. By trying this, the reception synchronization code F is detected within one transmission/reception cycle. After that, to prevent false synchronization,
Detection signal d output when detecting the received synchronization code F
As described above, the extraction timing of the reception synchronization code F is determined by counting a predetermined number of clocks, and at that extraction timing, the reception synchronization code F is successively extracted by a predetermined reference number n. After detection of
count).

Therefore, as shown in FIG. 7, the time required for the terminal device to start the counting operation (counting m, l) for detecting the synchronization code is equal to the number of displacements (shifts) in one conventional transmission/reception cycle. Instead of multiplying by the number of displacements (shifts) by one clock in synchronization with the received signal bits during synchronization code detection, add n times the one transmission/reception period necessary for synchronization code detection to prevent false synchronization mentioned above. It can be seen that the smaller the value of n is set, the greater the reduction in time compared to the conventional methods shown in FIGS. 1 and 6.

(g) Effects of the Invention As described above, according to the present invention, in the terminal device, the time required to establish synchronization at the time of starting communication is significantly shortened, and communication can be started promptly.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional synchronization detection circuit.
Fig. 2 is a diagram showing a synchronization detection circuit according to an embodiment of the present invention, Fig. 3 is a diagram showing a synchronization establishment sequence of the invention, Fig. 4 is a conceptual diagram of an uplink/downlink time division transmission system, and Fig. 5 6 is a diagram showing the conventional synchronization establishment sequence, FIG. 6 is a diagram showing the conventional operation sequence during synchronization code detection, and FIG. 7 is the operation during synchronization code detection and n consecutive detections of the present invention. It is a diagram showing a sequence. In the figure, 1 is a two-wire line, 2 is a two-wire/four-wire conversion circuit, 3 is a receiving circuit, 4 and 4' are separation circuits,
5 and 5' are synchronization code recognition circuits, 6 is a synthesis circuit,
7 is a synchronization code generation circuit, 8 is a transmission circuit, 9 is a transmission/reception switching counting circuit, 10 is a counting circuit, 11 and 13 are gates, 12 is a synchronous counting circuit, d is a detection signal, e
is the transmission/reception switching signal, g is the counting output, rc is the reception synchronization code F signal, rd is the reception data, sc is the transmission synchronization code F
signal, sd indicates transmitted data.

Claims (1)

[Scope of Claims] 1. In a terminal device accommodated in an automatic exchange via a two-wire line using an uplink and downlink time division transmission system, a synchronization code F is detected from a received signal transmitted from the automatic exchange. , a synchronization code detection means 5' that outputs a detection signal d, and 1 from the received signal until the detection signal d is received.
The extraction timing is shifted clock by clock and outputted to the synchronization code detection means 5', and after receiving the detection signal d, the synchronization code F is separated from the received signal at an extraction timing determined based on the detection signal d. separation means 4' for outputting to the synchronization code detection means 5'; transmission/reception switching means 9 for switching the transmission/reception timing based on the detection signal d; and transmission/reception switching means 9 for switching the transmission/reception timing until the detection signal d reaches a predetermined number n. 1. A synchronization detection circuit comprising: holding means 10 and 11 for suppressing switching from the terminal device to the transmitting state and holding the terminal device in the receiving state.