JPH0216825A - Frame synchronizer - Google Patents

Abstract

PURPOSE:To facilitate signal separation by storing a first frame synchronous bit string detection signal from a high-order group signal in a storage means and counting a clock corresponding to a low-order group transmission speed when an output from the storage means and a second frame synchronizing signal bit string detection signal from the high-order group signal are both inputted. CONSTITUTION:A parallel data signal from a serial-parallel conversion circuit 1 is transmitted to a frame synchronous circuit 2, is sampled at the low-order group transmission speed and is separated into low-order group signals. Frame synchronous strings F1 and F2 separated in two places in a multi frame are detected in detection circuits 3 and 4, and DFF6 or RSFF5 is set by a signal which is previously detected. Next, the signal F2 which has subsequently been detected is transmitted to FF6, and the AND with F1 stored in FF5 is taken by an AND gate 9, whereby it is transmitted to the input of FF6. The output value of FF6 is subsequently switched to synchronization and step-out, and a counter 7 is accordingly operated, whereby the pulse corresponding to the low-order group is counted only at the time of synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization device that separates PCM high-order group signals into low-order group signals.

[Prior art]

FIG. 2 shows a conventional circuit for performing frame synchronization when there are two frame synchronization bits in a multiframe.

In FIG. 2, reference numeral 21 denotes a serial-to-parallel conversion circuit, which converts the input high-order group PCM signal in a serial form into a parallel form. Reference numeral 22 denotes a frame synchronization circuit, which converts the signal from the serial-to-parallel conversion circuit 21 into a four-channel low-order group PC based on a frame synchronization signal from a frame synchronization pulse circuit, which will be described later.
Separate into M signals.

23 and 24 are Fl and F2 detection circuits that detect frame synchronization hit sequences Fl and F2 from the output signal of the serial/parallel conversion circuit 21, and when these detect a frame synchronization pattern (Fl comes first, F2 comes after), The result is stored in RS flip-flop 25.26. These detections are performed at different times, but since the results are recorded in Rs flip-flops 25 and 26, the AND gate 27 is opened only when a frame synchronization pattern is detected in both cases. Then, a signal is input to the D flip-flop 28.

D flip-flop 28 samples this input at a determined time and supplies a control signal to counter 29.

The counter 29 counts hits at the low-order group transmission rate and inputs the output to the frame synchronization pulse circuit 30.

The frame synchronization pulse circuit 30 inputs a frame synchronization signal for detecting a frame synchronization pattern to the Fl, F2 detection circuit 23.24 according to the input from the counter 29, and inputs a reset signal to the RS flip-flop 25.28. , a frame synchronization signal is input to the frame synchronization circuit 22.

[Problems to be Solved by the Invention] However, in the conventional circuit as described above, two RS flip-flops must be provided, and the circuit structure is complicated.

The object of the present invention is to provide a frame synchronization device that can solve the above-mentioned problems and separate PCM high-order group signals into low-order group signals with a simple configuration.

[Means for Solving the Problems] The present invention includes a means for recording a first frame synchronization bit string detection signal from a higher order group signal ↑5a, and an output of this storage means and a second frame synchronization bit string from the higher order group signal. and means for starting counting of clocks corresponding to the low-order group transmission rate when the detection signal is input together.

[Function] According to the present invention, counting of the clock corresponding to the low-order group transmission rate is started when the second frame synchronization bit string detection signal from the high-order group signal is also input.

[Embodiment] FIG. 1 shows an embodiment of the wooden invention. As shown in FIG. 1, a high-order group PCM signal is converted into a 4-bit parallel signal by a serial-to-parallel conversion circuit 1. The serial-to-parallel conversion circuit 1 operates at a high-order group transmission rate, and the output parallel signals are bit-shifted at the high-order group transmission rate.

The parallel data signal from the serial-to-parallel conversion circuit is sent to the frame synchronization circuit 2, sampled by this circuit 2 at a low-order group transmission rate, separated into low-order group signals, and output.

Frame synchronization bit strings F1 and F2, which are separated into two parts in the multiframe, are detected by an F1 detection circuit 3 and an F2 detection circuit 4, respectively. Since Fl is detected first, this F1 detection signal sets the D flip-flop 6.

Further, the F1 detection signal sets the RS flip-flop 5.

Next, when F2 is detected by the detection circuit 4, the F2 detection signal is sent to the flip-flop 6. This signal is ANDed with the F1 detection signal stored in the RS flip-flop 5 by the gate 9 and sent to the 0 input of the D flip-flop 6.

Through the above operation, the D flip-flop 6 switches the output value between the synchronous state and the out-of-synchronization state according to the cases in Table 1, which will be described later. This output is sent to the counter 7 as a control signal. According to this control signal, the counter
In a synchronized state, clock pulses corresponding to the low-order group transmission rate are counted, and in an out-of-synchronization state, counting is stopped.

According to the count value output of the counter 7, the frame synchronization pulse circuit 8 sends frame synchronization pulses to each component 3 according to the position of Fl in the multiframe, the position of F2, the frame synchronization state detection position, and the position of the RS flip-flop reset. 4. Output to 2.5. Further, the frame synchronization circuit 2 samples the data signal in accordance with the frame synchronization pulse, and thereby separates the data signal into low-order group signals arranged in regular channels and having frame phase synchronization.

In the embodiment shown in FIG. 1, there are two frame synchronization pins 1 to 1 in a multiframe. Table 1 shows the rules for achieving frame synchronization in this case.

〇 Match x Mismatch - 〇 on't Care Table 1 Cases of whether or not frame synchronization can be achieved based on the Fl and F2 detection results in a frame format with two frame synchronization bit strings in a multiframe. The frame synchronization bit string of F
l, and the rear frame synchronization bit string is F2. If both Fl and F2 do not match the predetermined frame synchronization pattern, synchronization is lost. Also, by detecting Fl first,
Suppose that F2 is detected after that.

Case 1 is a case where Fl is out of synchronization. In this case, the synchronization is out of synchronization regardless of the detection result of F2.

Case 2 is a case where F2 becomes out of synchronization even if Fl is in synchronization, and in this case, synchronization also occurs.

Case 3 is a case where both Fl and F2 are synchronized, and only then is it recognized that frame synchronization has been achieved.

In FIG. 1, the RS flip-flop 5 is a circuit for storing the F1 detection result, and is reset before the detection of F1.

For case 1, if Fl is out of sync, the RS flip-flop 5 remains reset, so its output remains out of sync. At this time, regardless of whether it is the detection result of F2, it is ANDed with the result of the RS flip-flop in the AND gate 9, so what is input to the D flip-flop 6 is an out-of-synchronization state.

For case 2 and case 3, the RS flip-flop is set according to the detection result of Fl. Therefore, the signal input to the D flip-flop 6 through the AND gate 9 is the same as the detection result of F2, and case 2,
Case 3 is realized.

The F1 output is input to the set terminal of the D flip-flop because the counter needs to count the number of bits up to the next F2 position at the same time as the frame synchronization pattern of Fl is detected. It is.

[Effects of the Invention] The tree invention makes it possible to separate high-order group signals in which frame synchronization bit strings are arranged at multiple locations in a multiframe into low-order group signals with an extremely simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the tree invention, and FIG. 2 is a block diagram of a conventional example.

Claims (1)

[Scope of Claims] A storage means for storing a first frame synchronization bit string detection signal from a higher order group signal, and when the output of the storage means and a second frame synchronization bit string detection signal from the higher order group signal are both input. 1. A frame synchronization device comprising: means for starting counting of a clock corresponding to a low-order group transmission rate.