JPH0477023A - Multi-frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by providing a counter means used selectively for a reference pulse generating means and a synchronization protection means with a selection signal. CONSTITUTION:A state transit counter 31 acts like a reference pulse generating means generating a reference pulse by a selection signal of a select signal generating circuit 41, a multi-frame pattern detection circuit 11 detects a multi- frame pattern in an input data to advance the counter 31 and when the counter counts up a prescribed number, a reference pulse is generated. On the other hand, a coincidence detection circuit 20 detects coincidence of the multi-frame pattern detection signal in the timing of the reference pulse and the counter 31 is switched by a selection signal of the select signal generating circuit 41 to act like a synchronization protection means and the counter counts the synchronization protection state.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a multi-frame synchronization circuit that detects and synchronizes a frame synchronization signal inserted into input data, and aims to provide a small and inexpensive multi-frame synchronization circuit. , a multi-frame pattern detection means for detecting a multi-frame pattern in input data; a reference pulse generation operation based on a multi-frame pattern detection signal outputted from the multi-frame pattern detection means; multi-frame pattern detection at the timing of the reference pulse; A counting means that performs a synchronization protection operation from the output of a coincidence detection circuit that detects coincidence or mismatch of signals, and a selection means that generates a selection signal used to switch the counting means between the reference pulse generation means and the synchronization protection means. do.

[Industrial application field]

The present invention relates to a multi-frame synchronization circuit that detects and synchronizes a frame synchronization signal inserted into input data.

Digital communication has become widely adopted, its communication speed has increased, and a wide variety of information has been multiplexed.

The scale of digital multiplexing devices for multiplexing a large amount of such various information and transmitting it at high speed is also increasing.

Such digital multiplexing devices are required to be miniaturized from the viewpoint of space and energy saving, and for this reason, it is necessary to miniaturize each component circuit.

[Conventional technology]

FIG. 5 shows a block diagram illustrating a conventional example.

The conventional example shown in FIG. 5 is a multi-frame pattern detection circuit 11 that detects multi-frame patterns in input data.
, a multi-frame counter 33 that counts the number of multi-frames from the multi-frame pattern detection signal of the multi-frame pattern detection circuit 11 and generates a reference pulse; 33, a coincidence detection circuit 20 that detects coincidence or mismatch of the multi-frame pattern detection signal of the multi-frame pattern detection circuit 11 at the timing of the reference pulse, and a coincidence detection circuit 20. A synchronization protection circuit 34 performs synchronization protection from the output of the multi-frame counter 33 and the protection circuit 3.
It is composed of a memory 32A that inputs and outputs the count value of 4.

11.12 of memory 32A is multi-frame counter 3
01.02 indicates the input terminal of the output signal of No. 3 and the input terminal of the output signal of the synchronization protection circuit 34, and 01.02 indicates the respective output terminal,
ADD is an address input terminal, and WE is a write enable input terminal.

In the above-described circuit, the multi-frame pattern detection circuit 11 detects a frame pattern in input data, and the multi-frame counter 33 is counted up based on the result.

For the count up, read the data at the specified address in the memory 32A, input it to the multi-frame counter 33, and set it to "1".
'' and writes the result to the same address in the memory 32A, and a reference pulse is generated when a specified number has been counted.

Matching or mismatching of the multi-frame pattern detection signals of the multi-frame detection circuit I11 is detected at the timing of the reference pulse output from the multi-frame counter 33, and the synchronization protection circuit 34 protects the synchronization based on the result and outputs the result.

To protect the synchronization, in the same way as counting up the multi-frame counter 33, data at a specified address in the memory 32A is read out, inputted to the synchronization protection circuit 34, incremented by "1", and the result is written to the same address in the memory 32A. This is done by doing this.

Further, the reset signal generation circuit 12 generates a reset signal when a multi-frame pattern is detected due to loss of synchronization.

[Problem to be solved by the invention]

In the conventional example described above, the multi-frame counter 33
Since the synchronization protection circuit 34 and two state transition counters are used, the circuit scale of the multiframe synchronization circuit becomes large.

An object of the present invention is to provide a small and inexpensive multiframe synchronization circuit.

[Means to solve the problem]

FIG. 1 shows a detailed diagram of the present invention.

In the block diagram of the principle of the present invention shown in FIG. 1, numeral 10 is a multi-frame pattern detection means for detecting a multi-frame pattern in input data, and 20 is a multi-frame pattern detection means for detecting a multi-frame pattern 110 at the timing of a reference pulse. This is a coincidence detection circuit that detects coincidence or mismatch of frame pattern detection signals.

Further, 30 is a counting means that generates a reference pulse from the multi-frame pattern detection signal outputted by the multi-frame pattern detection means 10 and performs a synchronization protection operation from the output of the minus number generating circuit 20; This selection means generates a selection signal for switching the counting means 30 between the reference pulse generation means and the synchronization protection means, and uses the selection signal generated by the selection means 40 to switch the counting means 30 between the reference pulse generation means and the synchronization protection means. This is a means to solve this problem.

(Function) A selection signal from the selection means 40 causes the counting means 30 to operate as a reference pulse generation means for generating a reference pulse, and the multi-frame pattern detection circuit 11 detects a multi-frame pattern in the input data and generates a reference pulse. The generating means is stepped and a reference pulse is generated when a predetermined number of counts has been counted up.

On the other hand, the minus number output circuit 20 detects coincidence or mismatch of the multi-frame pattern detection signals at the timing of the reference pulse, and the selection signal of the selection means 40 switches the counting means 30 to operate as a synchronization protection means, and the synchronization protection state is established. count.

In this way, the circuit scale can be reduced by switching the counting means 30 between the reference pulse generation means and the synchronization protection means using the selection signal generated by the selection means 40.

〔Example〕

The gist of the present invention will be specifically explained below with reference to Examples shown in Part 2 to FIG.

FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart of an embodiment of the present invention, and FIG. 4 is a diagram explaining state transition of an embodiment of the present invention. . Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 uses the same multi-frame pattern detection circuit 11, reset signal generation circuit 12, and counting means 30 as explained in the conventional example as the multi-frame pattern detection means 10 explained in FIG. , a state transition counter 31 and a memory 32 that inputs and outputs the count value.
In this example, the selection means 40 includes a select signal generation circuit 41 that generates a signal for switching the state transition counter 31 to a multi-frame counter and a synchronization protection circuit, and the same coincidence detection circuit 20 as described in the conventional example. .

i, 0 . ADD and WE indicate the same input/output terminals as the memory 32A described in the conventional example data.

The operation of the above circuit will be explained with reference to the time chart of FIG.

(2) Input data, HG indicates a handling group, and is composed of 12 frames.

(2) Indicates the result of detecting the multi-frame pattern of the input data (2) by the multi-frame pattern detection circuit 11, and outputs "0" upon multi-frame detection.

■ This is the address of the synchronization protection information and multiframe information written in the memory 32.

(2) This is a select signal generated by the select signal generation circuit 41, and the state transition counter 3 operates as a multi-frame counter when it is at a "low" level, and as a synchronization protection circuit when it is at a "high" level.

(2) The information at the address specified in (2) is read.

(2) The reset signal generation circuit 12 generates a recent signal based on the synchronization protection information that has continued in (2) and the multi-frame detection result in (2).

(2) At the "low" level of (2), it operates as a multi-frame counter, and enters the operation of (A) in FIG. 4, where the state transition counter 31 counts up and generates a reference pulse.

Therefore, the minus number output circuit 20 detects coincidence or mismatch from the reference pulse and the pattern detection result (2), and outputs the result.

When the subsequent synchronization protection information is read out, the signal {circle around (2)} becomes a "high" level, and the state transition counter 31 operates as a synchronization protection circuit and enters the operation shown in FIG. 4(B) and outputs the synchronization protection information.

(2) This is write data to the memory 32, where a is multi-frame information that has been transitioned by the state transition counter 31, and b is synchronization protection information that has been transitioned by the state transition counter 31.

(2) This is a write enable signal when writing data to the memory 32.

FIG. 4A shows the operation of the state transition counter 31 as a multi-frame counter, and is an example of a 6×2 decimal counter.

It increments by 1 during multi-frame detection, and returns to the state of 1101 when a multi-frame pattern is detected during out-of-synchronization.

FIG. 4B shows the operation of the state transition counter 31 as a synchronization protection circuit, and shows the protection states of the front four stages and the rear two stages.

HUNT in the figure means hunting, and indicates a state in which synchronization is established when the front four stages are out of synchronization.
5YNC indicates a synchronized state.

By configuring as described above, the multi-frame counter and the synchronization protection circuit can be configured in one circuit, and the circuit scale can be reduced.

〔Effect of the invention〕

According to the present invention as described above, by switching the state transition counter to the multiframe counter and the synchronization protection circuit, it is possible to provide a small-scale multiframe synchronization circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart of an embodiment of the present invention, and FIG. 4 is a block diagram explaining the present invention in detail. FIG. 5, which explains the state transition of the embodiment of the invention, shows a block diagram which explains the conventional example. In the figure, IO is a multi-frame pattern detection means, 11 is a multi-frame pattern detection circuit, 12 is a reset signal generation circuit, 20 is a coincidence detection circuit, 30 is a counting means, 31 is a state transition counter, 32. 32A is a memory, 33 34 is a synchronization protection circuit, 40 is a selection means, and 41 is a select signal generation circuit, respectively. Figure 1 is a block diagram explaining the details of the present invention. Figure 2 is a block diagram explaining the details of the present invention. W4
[Ha1] Ryo, Dey3 (, DeJmo) Nikan et al.

Claims (1)

[Claims] A multiframe synchronization circuit that detects and synchronizes a frame synchronization signal inserted in input data, the circuit comprising multiframe pattern detection means (10) for detecting a multiframe pattern in the input data. ), and a coincidence detection circuit (10) that generates a reference pulse from the multi-frame pattern detection signal outputted from the multi-frame pattern detection means (10) and detects coincidence or mismatch of the multi-frame pattern detection signal at the timing of the reference pulse. Counting means (3) performs synchronization protection operation from the output of
0); and selection means (40) for generating a selection signal for switching use of the counting means (30) between reference pulse generation means and synchronization protection means.