JPH03204732A - Information processor - Google Patents

Abstract

PURPOSE:To prevent a fault from being repeated by providing separately a fault detecting circuit, deciding a fault to be a light fault, when a fault cannot be detected by the fault detecting circuit and deciding a fault to be a heavy fault, when the fault is detected, and reporting them to a host device. CONSTITUTION:The fault at the time when a read-out operation of a memory device 4 in a processor part 5 is executed in detected, and the fault is reported to a diagnostic processor part 6. The diagnostic processor part 6 switches it to a diagnostic address bus in order to execute diagnostic read-out to the memory device 4, and holds an address in which a fault is generated. Subsequently, by the diagnostic address bus, the address in which the fault is generated is read out, and when the fault is not detected by a fault detecting circuit 10, the diagnostic processor part 6 decides that the fault is a light fault, sends out an initializing instruction to the processor part 5, and on the other hand, when the fault is detected, the diagnostic processor part 6 decides that its fault is a heavy fault, and reports an operation stop to the host device. In such a manner, the fault can be diagnosed without repeating a fault processing at the time when the fault is generated.

Description

[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for failure processing of an information processing apparatus.

The present invention relates to failure handling when accessing a memory device.

〔overview〕

The present invention includes a processor unit that executes software instructions;
In an information processing device equipped with a diagnostic processor unit that performs diagnostic control of the processor unit, separate hardware is provided to detect the occurrence of a failure, and when this hardware detects the occurrence of a failure, the failure is immediately recognized as a minor failure. However, by determining whether it is a serious failure and determining the subsequent operation, it is possible to eliminate the repetition of recovery processing and improve the reliability of information processing.

[Conventional technology]

Conventionally, this type of failure handling is such that when a failure is detected when accessing a memory device, the diagnostic processor section issues an initialization instruction to the processor section, restores the initial state, and continues processing (recovery processing), so that the failure occurs again. Even if a failure is detected when accessing an address, the process is returned to the initial state and processing continues, and after repeating this recovery process many times, it determines that the failure is a serious failure and stops the processor. Ta.

In addition, in some types of fault processing, when a fault is detected during operation, the upper device stores the important part in the memory device and uses it as fault information, and when the content of the important part of the memory device is read out, it is read out. When a data failure occurs, the diagnostic processor section detects a serious failure and stops the processor section.

[Problem that the invention seeks to solve]

In the conventional fault handling described above, when a fault is detected, the diagnostic processor section determines that the fault is a minor fault, sends an initialization instruction to the processor section to recover the processor section, and repeats the recovery process over and over again. After repeated operations, the failure was determined to be a serious failure and the operation of the processor section was stopped, resulting in a significant drop in reliability.

The present invention is intended to solve such problems, and aims to provide a device that can determine failures and determine subsequent operations without repeating recovery processing operations, thereby improving reliability.

[Means for solving problems]

The present invention includes a software control unit, an arithmetic processing unit, a memory device, a memory control unit, and a read data register that temporarily stores data read from the memory device, and includes a processor unit that executes software instructions, and a processor unit that executes software instructions. In the information processing apparatus, the processor section includes a fault detection circuit that detects a fault when a read operation of the memory device is executed, and the fault detection circuit detects a fault. an error display flip-flop that reports a failure to the diagnostic processor section when detected; and a diagnostic address bus under control of the diagnostic processor section when performing diagnostic reading from the diagnostic processor section to the memory device. It is characterized by including an address selector for switching connection and an address register for holding an address where a failure has occurred.

means for the diagnostic processor to read an address where a fault has occurred from the diagnostic address bus and determine whether the fault is a major fault or a minor fault based on whether the fault detection circuit has detected a fault; It is preferable to include means for reporting an operation stoppage to a host device of the diagnostic processor unit when the failure is determined to be a serious failure, and means for sending an initialization instruction to the processor unit when the failure is determined to be a minor failure. .

[Effect]

A failure is detected when a read operation of a memory device within the processor unit is executed, and the failure is reported to the diagnostic processor unit. The diagnostic processor section switches to the diagnostic address bus to perform diagnostic reading on the memory device, and holds the address where the fault has occurred. Next, the address where the fault has occurred is read by the diagnostic address bus, and if the fault is not detected by the fault detection circuit, the diagnostic processor section determines the fault to be a minor fault, sends an initialization instruction to the processor section, and When a failure is detected, the diagnostic processor section determines the failure to be a serious failure and reports that the operation has stopped to the host device.

As a result, a fault can be diagnosed without repeating fault processing when a fault occurs, and reliability can be improved.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention includes a software control section 1, an arithmetic processing section 2,
, memory device 4, memory control unit 3, and memory device 4
The processor section 5 includes a read data register 8 that temporarily stores data read from the processor section 5, and a diagnostic processor section 6 that performs diagnostic control of the processor section 5. , a fault detection circuit 10 that detects a fault when a read operation of the memory device 4 is executed, and an error display flip-flop that reports the fault to the diagnostic processor section 6 when a fault is detected by the fault detection circuit 10. 9, and an address selector 11 that is switched and connected to the diagnostic address bus under the control of the diagnostic processor section 6 when performing diagnostic reading from the diagnostic processor section 6 to the memory device 4;
Address register 7 that holds the address where the failure occurred
Further, the diagnostic processor reads the address where the fault has occurred via the diagnostic address bus 54, and determines whether the fault is a major fault or a minor fault depending on whether the fault detection circuit 10 detects the fault. means for determining the failure to be a serious failure, means for reporting the operation stoppage to a higher-level device (not shown) of the diagnostic processor unit 6 when the failure is determined to be a serious failure, and means for issuing an initialization instruction to the processor unit 5 when the failure is determined to be a minor failure. and means for transmitting.

Next, the operation of the embodiment of the present invention configured as described above will be explained. FIG. 2 is a flowchart showing the operation flow of the diagnostic processor section 6 according to the embodiment of the present invention.

When the memory device 4 has necessary data, the software control unit 1 sends a read request to the memory control unit 3 through the control line 51 and controls the arithmetic processing unit 2 through the control line 52. The address is sent to the address register 7 via the address line 53.

The memory control unit 3 controls the address selector 11 via the control line 62 to store the address in the address register 7, reads the memory device 4 via the address line 55 which is the output of the address register 7, and uses the output data 56 as read data. Store it in register 8. The stored data is sent to the arithmetic processing unit 2 through the data line 57 and processed.

Next, the operation when a failure other than memory occurs will be explained.

The diagnostic processor section 6 sends a diagnostic read request to the memory control section 3 through a control line 60 in order to store important parts in the memory device 4, and sends an address to the address register 7 through a diagnostic address bus 54. When the memory control unit 3 accepts the diagnostic read request, it switches the address selector 11 to the diagnostic read side and stores it in the address register 7.

The memory device 4 is accessed to the address stored in the address register 7, and the output data 56 is read out.
The data is stored in the read data register 8.

The stored data is sent to the diagnostic processor section 6 via the data line 57, and is sent to a host device (not shown) via the data line 64 as needed. This operation is repeated until the required portion is stored in the host device.

After the storage process is completed, the diagnostic processor section 6
An initialization instruction is sent to the controller through the control line 61, and the software control unit 1, arithmetic processing unit 2, and memory control unit 3 are set to their initial states and processing is restarted.

Next, the operation when a memory failure occurs will be explained.

When the software control unit 1 has the necessary data in the memory device 4, it issues a read request to the memory control unit 3 through the control line 51, and sends an address to the address register 7 through the control line 52.

The memory control unit 3 controls the address selector 11 through the control line 62 to store the address in the address register 7, and the diagnostic address bus 5, which is the output of the address register 7,
4 reads out the memory device 4 and its output data 56
is read out, and the output data is checked by the failure detection circuit 10.

If a fault is detected at this time, the error display flip-flop 9 lights up and the control line 59 is passed to the diagnostic processor section 6.
A failure is reported. At the same time, the address accessed through the address line 55 is saved in the diagnostic processor section 6,
When the diagnostic processor section 6 receives the report from the error display flip-flop 9, it sends a diagnostic read request to the memory control section 3 through the control line 60, and stores the address saved through the diagnostic address bus 54 in the address register 7.
send to

When the memory control unit 3 accepts the diagnostic read request, it switches the address selector 11 to the diagnostic read side and stores it in the address register 7. The memory device 4 is accessed with respect to the address stored in the address register 7, the output data 56 is read out, and the output data 56 is checked by the fault detection circuit 10.

If no error is detected as a result of the check (
ERRD-ERR), the diagnostic processor unit 6 determines this to be a minor failure, stores the important part in the memory device 4 in the same way as it would do when a failure occurs in a device other than the memory device 4, and then stores the important part in the processor unit 5. In response, an initialization instruction is sent through the control line 61, the software control section 1, the arithmetic processing section 2, and the memory control section 3 are set to the initial state, and the process is restarted.

If an error is detected (ERRD-ERR), the diagnostic processor section 6 determines that it is a serious failure, and stores the important parts in the memory device 4 in the same manner as when a failure other than the memory device 4 occurs. , an initialization instruction is not sent to the processor unit 5, but the host unit is notified via the control line 63 that the operation is in a stopped state.

〔Effect of the invention〕

As explained above, according to the present invention, instead of executing the recovery process that has been performed multiple times in response to a failure when accessing a memory device, it is determined that a single failure is a minor failure or a serious failure, and then the recovery process is performed. This has the effect of determining the operation of the system and increasing reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a flowchart showing the flow of operation of the diagnostic processor unit according to the embodiment of the present invention. 1... Software control unit, 2... Arithmetic processing unit, 3
...Memory control section, 4.Memory device, 5.Processor section, 6.Diagnostic processor section, 7.Address register, 8.Read data register, 9..
・Error display flip-flop, 10...fault detection circuit, 11...address selector.

Claims (1)

[Claims] 1. A processor unit that executes software instructions, including a software control unit, an arithmetic processing unit, a memory device, a memory control unit, and a read data register that temporarily stores data read from the memory device. and a diagnostic processor section that performs diagnostic control of the processor section, wherein the processor section includes a fault detection circuit that detects a fault when a read operation of the memory device is executed; an error display flip-flop that reports a fault to the diagnostic processor section when a fault is detected by the circuit; and an error display flip-flop that reports the fault to the diagnostic processor section when a fault is detected by the circuit; An information processing device comprising: an address selector that is switched and connected to a diagnostic address bus; and an address register that holds an address where a failure has occurred. 2. Means for the diagnostic processor to read an address where a fault has occurred from the diagnostic address bus, and determine whether the fault is a major fault or a minor fault based on whether the fault detection circuit has detected a fault. The information processing device according to claim 1, comprising: 3. Means for the diagnostic processor to report an operation stoppage to a host device of the diagnostic processor unit when the failure is determined to be a serious failure, and to send an initialization instruction to the processor unit when the failure is determined to be a minor failure. 3. The information processing apparatus according to claim 2, further comprising means.