JPH0776948B2 - Failure diagnosis method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure diagnosing method , and in particular, in a high-reliability computer system in which buses are duplicated, in order to solve the difficulty of investigating the cause when a bus error occurs, each bus is independent. A fault diagnosing method that makes it possible to easily isolate the failure point by inferring the failure point from the error information provided by providing a register that can be accessed by using the bus. <Br / > Yes.

In a general system, when a bus error occurs in the system bus that constitutes a computer due to a failure of the system bus or the like, the computer may go down in an unknown state. If you predict the system down in advance, you can investigate the faulty part of the bus when the system is stopped, but in a high-reliability system that does not allow the system to stop, you cannot stop the system and investigate the cause. . Therefore, there is a need for a means for investigating the location of failure without stopping the operation.

[0003]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional high-reliability system, and FIG. 7 is a timing chart for explaining a failure. Generally, in a high reliability system, a plurality of functional units (microprocessors etc.) having the same function are connected in parallel, and these are connected in parallel to a plurality of buses. As shown in (A), a bus 1 for the active system and a bus 2 for the standby system are provided, and in the case of a failure, a configuration is adopted in which one of the buses is switched to maintain the operation and the system does not go down. Each functional unit 1, 2, 3, ... Including a host computer (CPU) is connected to both buses 1 and 2 via an internal bus switching unit SW.
In the normal state, the bus switching unit SW is connected to the bus 1 side under the control of the bus control unit BC. For example, the processing access from the functional unit 1 is performed by the bus 1 as shown by the solid line.
Through a predetermined functional unit (for example, functional unit 3)
Is processed by the processing unit. Therefore, in the conventional configuration, the bus control unit is connected only to the connected bus side.

If a bus error occurs at "X" on the bus 1, a bus error message is sent and then the bus 1 is recorded as a failure state as shown in (B). By separating from the processing and performing all the processing using the bus 2, the processing is continued without the system going down. That is, since the path indicated by the dotted line of the bus 1 is out of order, the bus switching unit SW is switched to connect to the bus 2 side to send the processing access to the functional unit 3. As described above, in the high-reliability system, each functional unit has a bus switching function, and the processing is continued without the system going down to ensure high reliability.

FIG. 8 is a flow chart for processing a bus error. When a bus error occurs, error information is logged (step 1), the bus 1 in which the bus error has occurred is switched to the standby bus 2 (step 2), and then the processing access is retried (step 3). ), It is determined whether or not the retry is successful (step 4), and if the retry is successful (YES), the access process is continued (step 5). However, if the retry is unsuccessful in step 4 (NO), error information is logged (step 6) and the system goes down (step 7).

[0006]

However, as described above, in the configuration in which the bus is simply switched from the active system to the standby system when a failure occurs, all the functional units are connected to the bus 2 which is executing processing. Therefore, if there is a failure in each functional unit, it is possible to access it for investigative diagnosis. However, for example, in the case of a failure of a bus driver (not shown) between the bus and the functional unit, the bus 1 is used to access the register R of the functional unit. Even if an attempt is made, no response is returned, so that there is a problem that it is not possible to investigate where the failure occurred without knowing where the failure occurred.

On the other hand, FIG. 9 shows a conventional fault investigation access method that addresses the above problems. Bus 1 as shown
Suppose that the processing access is once ended by using the bus 2 while the CPU is in failure, after switching the bus switching units SW of all the functional units to the failed bus 1 side after the processing is completed, the CPU
A special command is sent from the functional unit 1 including the above, each functional unit is switched to the bus 1, the registers of each functional unit are sequentially accessed, the failure location judgment is notified, and finally the bus 2 is switched to the next I am trying to process it. Here, the special command is, for example, a bus simultaneous switching command used for DMA bus switching.

However, in this method, as shown in the figure, while each register is being accessed, the stop time is until the next processing, which is a problem in a high-reliability system that does not allow temporary suspension of processing. It is an object of the present invention to provide a failure diagnosis method capable of performing a failure diagnosis investigation without interrupting a process during access in the failure diagnosis of a high reliability system.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention is a bus 1 for the active system and a bus 2 for the standby system.
In a high-reliability system in which a plurality of functional units 1 to 3 are connected to both of the buses to provide a redundant configuration,
One of the functional units is used as a service processor, or a service processor 4 (FIG. 2) shared by the active bus and the standby bus is provided, and further, the bus control means BC and A maintenance register HR connected to the bus control means is provided, and a pair of the bus control means and the maintenance register is provided on each of the active system bus and the standby system bus. The maintenance register of each functional unit is accessed through the faulty bus, and the location of the bus error is estimated from the access result.

[0010]

According to the present invention, one of the functional units is provided with the function of the service processor, or a new service processor is connected, and the maintenance register in each functional unit is passed through the faulty bus using this service processor. By referring to this, the investigation diagnosis is performed while continuing the processing access on another bus.

[0011]

FIG. 2 is a block diagram of an embodiment of the present invention.
Is a processing timing chart of the present invention. In the figure, 4 is a service processor (SVP), which is connected to the active bus 1 or the standby bus 2 by an internal bus switching unit SW. HR is a maintenance register and is built in all functional units 1 to 3 except the service processor 4 together with the bus control unit BC. Moreover, as shown in the drawing, it is provided for each of the buses 1 and 2 in each functional unit. Therefore, the maintenance register HR can be accessed from both buses regardless of the connection state of the functional units.

Further, the service processor 4 may be a processor equivalent to other functional units. Then, as illustrated, the bus switching units SW of the functional units 1 to 3 are connected to the non-failed bus 2 side, but the bus switching unit SW of the service processor 4 is connected to the failed bus 1 side. Has been done. By connecting in this way, it is possible to perform fault diagnosis access from the service processor side via the faulty bus 1 without conflicting with process access.

When a bus error "X" occurs during access processing using the bus 1 as shown in FIG. 3, the processing is switched to the bus 2 and the processing is continued. It is possible to perform the failure investigation by using the bus 1 of No. 1 so that the processing access and the investigation access do not conflict with each other. That is, the service processor 4 operates independently of the processing access, accesses the maintenance register HR from the service processor 4 using the faulty bus 1, and determines whether or not there is a bus error at the time of access and the maintenance register HR. Check the recorded bus error detection history information and so on. When the registers of a plurality of functional units detect a bus error or generate a bus error during access, the bus itself is in failure, and only one functional unit register detects a bus error or generates a bus error during access. If so, it is determined that the functional unit is in failure.

FIG. 4 is a block diagram of an embodiment of the maintenance register of the present invention. As shown in the figure, an error detection history defines an adapter error, a control bus error, a data bus error, an address bus error, etc., and a storage space for each error is provided, and a switching state display space is further provided. Then, a space for displaying each functional unit (adapter) type is provided.

FIG. 5 is a processing flowchart of an embodiment of the present invention. As described above, the maintenance register is accessed from the service processor. First, each adapter is accessed from the service processor (step 1) and it is determined whether a bus error has occurred (step 2). If (YES), the adapter in which the bus error has occurred is recorded (step 3).

On the other hand, if no bus error has occurred (NO), the contents of the maintenance register are recorded (step 4), then it is judged whether all adapters have been accessed (step 5), and all adapters are accessed. If not (N
O) Return to step 1, and if all the adapters are accessed (YES), then it is determined whether there is a plurality of adapters in which a bus error has occurred (step 6). If there are multiple adapters (YES). It is determined that the motherboard, that is, the system bus has failed, and a message prompting replacement of the service processor or a motherboard to which a plurality of adapters are connected is displayed (step 7). If only one adapter is available (N
O), the service processor displays a message prompting the replacement of the adapter having the bus error (step 8), and
A display prompting replacement of the adapter in which the adapter error is displayed is displayed (step 9).

In the case of a failure of the bus itself, the system must be suspended in order to replace the motherboard as described above, but as a practical matter, the failure rate of the motherboard is very low, and the effect of step 7 Can be almost ignored.

[0018]

As described above, according to the present invention,
In a high-reliability system, even if a failure occurs in the working bus, the failure location can be investigated and diagnosed without stopping the system while continuing the processing in the high-reliability system. It is possible to significantly reduce the time, and to provide highly reliable service.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a processing timing chart of the present invention.

FIG. 4 is a configuration diagram of a maintenance register according to an embodiment of the present invention.

FIG. 5 is a processing flowchart of an embodiment of the present invention.

FIG. 6 is a conventional configuration diagram.

FIG. 7 is a conventional processing timing chart.

FIG. 8 is a conventional processing flowchart.

FIG. 9 is a processing timing chart for explaining conventional measures.

[Explanation of symbols]

 1 to 3 ... Functional unit 4 ... Service processor SW ... Bus switching unit BC ... Bus control unit HR ... Maintenance register CPU ... Host computer SVP ... Service processor

Claims (4)

[Claims] 1. A high-reliability system in which an active bus (1) and a standby bus (2) are arranged, and a plurality of functional units (1 to 3) are connected to both of the buses to provide a redundant configuration. In the above, any one of the functional units is used as a service processor, and the bus control means (B
C) and a maintenance register (H) connected to the bus control means.
R) and a pair of the bus control means and the maintenance register is provided on each of the active bus and the standby bus, the service processor stores the maintenance register of each functional unit at the time of fault investigation and diagnosis. A fault diagnosis method characterized in that access is made via a faulty bus and the location of the bus error is estimated from the access result. 2. A high-reliability system in which a working bus (1) and a standby bus (2) are arranged, and a plurality of functional units (1-3) are connected to both buses to form a redundant configuration. In the above, a service processor (4) shared by the active bus and the standby bus is connected, and further, a bus control means (BC) and a maintenance register (HR) connected to the bus control means in each functional unit. And a pair of the bus control means and the maintenance register is provided on each of the active bus and the standby bus, and the service processor is in failure of the maintenance register of each functional unit when investigating and diagnosing the failure. The method for diagnosing a failure is characterized in that the location of the bus error is estimated from the access result by accessing via the bus. 3. The maintenance register stores an adapter error, a control error, a data bus error, and an address bus error as an error detection history.
The failure diagnosis method described in. 4. The failure diagnosis method according to claim 1, wherein the maintenance register further stores a display of a switching state and a display of an adapter type.