JPH03201593A - Multilayer wiring circuit module - Google Patents

Multilayer wiring circuit module

Info

Publication number
JPH03201593A
JPH03201593A JP1343629A JP34362989A JPH03201593A JP H03201593 A JPH03201593 A JP H03201593A JP 1343629 A JP1343629 A JP 1343629A JP 34362989 A JP34362989 A JP 34362989A JP H03201593 A JPH03201593 A JP H03201593A
Authority
JP
Japan
Prior art keywords
film
capacitor
circuit module
wiring
sheets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1343629A
Other languages
Japanese (ja)
Inventor
Mitsuaki Yamakawa
山川 光明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Lighting and Technology Corp
Original Assignee
Toshiba Lighting and Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Lighting and Technology Corp filed Critical Toshiba Lighting and Technology Corp
Priority to JP1343629A priority Critical patent/JPH03201593A/en
Publication of JPH03201593A publication Critical patent/JPH03201593A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a film having excellent heat resistance and high permittivity by providing a dielectric film formed by kneading fine powder material having high permittivity and organic polymer insulating material having heat resistance in a sheet state, and electrodes formed at least on one side surface of the ferroelectric film. CONSTITUTION:Through holes 2 are formed previously through a board 1. Both side surfaces of the board 1 are printed with conductive paste, and dried to be formed with an upper electrode 4 of a capacitor and a wiring layer 5. Similarly, a unit wiring sheet 8 printed with a lower electrode 7 of the capacitor is formed on a thermoplastic material 6, fine powder material having high permittivity and organic polymer insulating material having heat resistance are kneaded, and disposed on an inner layer in the form of a dielectric film 9. Then, a plurality of the sheets 8 and the films 9 are laminated, and thermally press-bonded thus producing a multilayer wiring circuit module containing a capacitor formed of the electrodes 4, 7 and the film 10.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、特に内層にコンデンサ素子を内蔵した多層配
線回路モジュールに関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention particularly relates to a multilayer wiring circuit module having a built-in capacitor element in an inner layer.

(従来の技術) 近年、電子機器の小型化、多機能化が急速に進み、これ
に伴って部品は小型化、薄膜化し、更に回路も複雑にな
るため、同一平面内での配線は困難になってきている。
(Conventional technology) In recent years, electronic devices have rapidly become smaller and more multifunctional, and as a result, components have become smaller and thinner, and circuits have become more complex, making it difficult to wire them on the same plane. It has become to.

このため、厚膜印刷、グリーンシート多層、スルホール
多層等の種々の配線の多層化が行なわれ、夫々実用化さ
れてるようになってきている。
For this reason, various types of wiring multilayering, such as thick film printing, green sheet multilayering, through-hole multilayering, etc., have been carried out, and each has come into practical use.

ところで、部品を基板内に内蔵し、多層化技術により配
線形成すると、回路モジュールを更に小型化する事がで
きる。最近、こうした回路モジュールとして、熱可塑性
基板とこの基板の片面又は両面に形成された導体配線パ
ターンとからなる単位配線シートを複数枚重ねて一体形
成した多層印刷配線板において、該誘電体フィルムの両
面に電極を形成配置した回路が提案されている。
By the way, if components are built into the board and wiring is formed using multilayer technology, the circuit module can be further miniaturized. Recently, as such a circuit module, a multilayer printed wiring board that is integrally formed by stacking a plurality of unit wiring sheets each consisting of a thermoplastic substrate and a conductor wiring pattern formed on one or both sides of this substrate, is being used. A circuit in which electrodes are formed and arranged has been proposed.

第1図(A)〜(C)は、多層配線回路モジュールの製
造方法の一例を工程順に示す断面図である。
FIGS. 1A to 1C are cross-sectional views showing an example of a method for manufacturing a multilayer wiring circuit module in the order of steps.

■まず、シート状に形成した熱可塑性樹脂製絶縁基板1
を用意する。ここで、基板1には予めスルホール2が設
けられており、図中の3は基板表面のランドである(第
1図(A)図示)。
■First, a thermoplastic resin insulating substrate 1 formed into a sheet shape
Prepare. Here, a through hole 2 is provided in advance in the substrate 1, and 3 in the figure is a land on the surface of the substrate (as shown in FIG. 1(A)).

■次に、前記絶縁基板1の両面に導電性ペーストを印刷
、乾燥し、後記コンデンサの上部電極4と配線層5を形
成する。また、同様に熱可塑性基材6上にコンデンサの
下部電極7を印刷した単位配線シート8を形成し、誘電
体フィルム9を内層に配置した(第1図(B)図示)。
(2) Next, a conductive paste is printed on both sides of the insulating substrate 1 and dried to form an upper electrode 4 and a wiring layer 5 of a capacitor, which will be described later. Similarly, a unit wiring sheet 8 on which the lower electrode 7 of a capacitor was printed was formed on a thermoplastic substrate 6, and a dielectric film 9 was placed on the inner layer (as shown in FIG. 1(B)).

なお、前記配線層は絶縁基板及び熱可塑性基材5の両面
に形成した場合について述べたが、誘電体フィルムの両
面に形成しても良い。また、誘電体フィルムには予め孔
を設けておき、該誘電体シートをはさんで相互に接続で
きる様に加工しても良い。次いで、上記のようにして得
られた単位配線シート8と誘電体フィルム9を複数枚積
層する。
Although the wiring layer is formed on both sides of the insulating substrate and the thermoplastic base material 5, it may be formed on both sides of the dielectric film. Alternatively, holes may be provided in the dielectric film in advance and processed so that the dielectric sheets can be sandwiched and connected to each other. Next, a plurality of unit wiring sheets 8 and dielectric films 9 obtained as described above are laminated.

■次いで、こうした状態で熱プレスにより加熱圧着し、
内部にコンデンサlOを内蔵した多層配線回路モジュー
ルを製造する(第1図(C)図示)。
■Next, in this state, heat and pressure bonding is carried out using a heat press,
A multilayer wiring circuit module having a built-in capacitor IO is manufactured (as shown in FIG. 1(C)).

しかしながら、従来の多層配線回路モジュールによれば
、コンデンサの特性から見ると、誘電体フィルムの誘電
率は3〜5であり、−層の厚さを薄くするにも眼光があ
り、1素子当りの容量は比較的小さく、大容量コンデン
サを形成するのは難しい。
However, according to the conventional multilayer wiring circuit module, the dielectric constant of the dielectric film is 3 to 5 when viewed from the characteristics of the capacitor. The capacitance is relatively small and it is difficult to form large capacitance capacitors.

(発明が解決しようとする課題) 本発明は上記事情に鑑みてなされたもので、従来よりも
耐熱性が良くかつ誘電率の高いフィルムの形成を可能と
し、大容量のコンデンサを形成しえる多層配線回路モジ
ュールを提供することを目的とする。
(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and it enables the formation of a film with better heat resistance and higher dielectric constant than conventional ones, and is capable of forming a multilayer capacitor with a large capacity. The purpose is to provide a wired circuit module.

[発明の構成] (課題を解決するための手段と作用) 本発明は、熱可塑性絶縁基板と、この絶縁基板の少なく
とも片面側に一体的に設けられ、主面に配線パターンを
形成した複数の単位配線シートと、前記絶縁基板とシー
ト間またはシート同士間に設けられ、高誘電率を有する
微細粉末材料及び耐熱性を有する有機高分子絶縁材料を
混練りしシート状にしてなる誘電体フィルムと、この強
誘電体フィルムの少なくとも片面に形成された電極とを
具備したことを特徴とする多層配線回路モジュールであ
る。
[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention includes a thermoplastic insulating substrate and a plurality of thermoplastic insulating substrates that are integrally provided on at least one side of the insulating substrate and have a wiring pattern formed on the main surface. A unit wiring sheet, and a dielectric film which is provided between the insulating substrate and the sheets or between the sheets and is formed into a sheet by kneading a fine powder material having a high dielectric constant and an organic polymer insulating material having heat resistance. , and an electrode formed on at least one side of the ferroelectric film.

本発明において、前記絶縁基板の材質としては、例えば
ポリ塩化ビニル、ポリスチレン、飽和ポリエステル樹脂
、ポリエチレン、ポリプロピレン、ポリカーボネート、
ポリフェニレンオキサイド、ポリスルフォン、ポリフェ
ニレンサルファイド、ポリアセタール、ポリアミド等の
熱可塑性樹脂が挙げられる。
In the present invention, the material of the insulating substrate includes, for example, polyvinyl chloride, polystyrene, saturated polyester resin, polyethylene, polypropylene, polycarbonate,
Examples include thermoplastic resins such as polyphenylene oxide, polysulfone, polyphenylene sulfide, polyacetal, and polyamide.

本発明において、前記単位配線シート主面に形成される
配線パターンは前記絶縁基板上に導電性ペーストを印刷
、乾燥する事により形成されるが、前記導電性ペースト
としては上記熱可塑性樹脂あるいは他の熱可塑性樹脂を
バインダーとしてこれと金属粉体を混練り、調整したも
のを用い、必要があれば溶剤を適宜添加する。ここで、
前記金属粉体としては、銀、銅、ニッケル、白金、アル
ミニウム等のいずれを用いてもよいが、導電性、経済性
の点を考慮すると銅、銀が好ましい。
In the present invention, the wiring pattern formed on the main surface of the unit wiring sheet is formed by printing and drying a conductive paste on the insulating substrate. A mixture prepared by kneading a thermoplastic resin as a binder with metal powder is used, and a solvent is appropriately added if necessary. here,
As the metal powder, any of silver, copper, nickel, platinum, aluminum, etc. may be used, but copper and silver are preferable in terms of conductivity and economy.

本発明において、高誘電率を有する微細粉末材料として
は、例えばチタン酸バリウム系、チタン酸ストロンチウ
ム系、酸化チタン系、酸化タンタル系、酸化アルミニウ
ム系等の無機質材料が挙げられる。これらの材料の粒径
は、約0,1〜5μmがよい。後記有機高分子絶縁材料
に対する誘電率材料の混合比は、用いる材料により異な
るが、重量比で0.5〜5:5〜9,5である。従って
、誘電体フィルムの誘電率を大きくするには、前記無機
質材料等の割合を大きくすればよい。
In the present invention, examples of the fine powder material having a high dielectric constant include inorganic materials such as barium titanate, strontium titanate, titanium oxide, tantalum oxide, and aluminum oxide. The particle size of these materials is preferably approximately 0.1 to 5 μm. The mixing ratio of the dielectric constant material to the organic polymer insulating material described below varies depending on the materials used, but is in the range of 0.5 to 5:5 to 9.5 by weight. Therefore, in order to increase the dielectric constant of the dielectric film, the proportion of the inorganic material etc. may be increased.

本発明において、耐熱性を有する有機高分子絶縁材料と
しては、ポリフェニレンサルファイド、ポリブチレンテ
レフタレート、ポリエチレンテレフタレート、ポリカー
ボネート樹脂等が挙げられる。
In the present invention, examples of heat-resistant organic polymer insulating materials include polyphenylene sulfide, polybutylene terephthalate, polyethylene terephthalate, polycarbonate resin, and the like.

次に、本発明に係る多層配線回路モジュールの製造方法
について説明する。
Next, a method for manufacturing a multilayer wiring circuit module according to the present invention will be explained.

■まず、シート状に形成した熱可塑性樹脂製絶縁基板1
を用意する。ここで、基板1には予めスルホール2が設
けられており、図中の3は基板表面のランドである(第
1図(A)図示)。
■First, a thermoplastic resin insulating substrate 1 formed into a sheet shape
Prepare. Here, a through hole 2 is provided in advance in the substrate 1, and 3 in the figure is a land on the surface of the substrate (as shown in FIG. 1(A)).

■次に、前記絶縁基板1の両面に導電性ベーストを印刷
、乾燥し、後記コンデンサの上部電極4と配線層5を形
成する。また、同様に熱可塑性基材6上に後記コンデン
サの下部電極7を印刷した単位配線シート8を形成し、
高誘電率を有する微細粉末材料及び耐熱性を有する有機
高分子絶縁材料を混練りしシート状にしてなる誘電体フ
ィルム9を内層に配置する(第1図(B)図示)。なお
、前記配線層は絶縁基板1及び熱可塑性基材5の両面に
形成した場合について述べたが、誘電体フィルム9の両
面に形成しても良い。また、誘電体フィルム9には予め
孔を設けておき、該誘電体シートをはさんで相互に接続
できる様に加工しても良い。次いで、上記のようにして
得られた、熱プレスにより加熱圧着する。
(2) Next, a conductive base is printed on both sides of the insulating substrate 1 and dried to form an upper electrode 4 and a wiring layer 5 of a capacitor, which will be described later. Similarly, a unit wiring sheet 8 on which a lower electrode 7 of a capacitor described later is printed is formed on a thermoplastic base material 6,
A dielectric film 9 made of a sheet formed by kneading a fine powder material having a high dielectric constant and an organic polymer insulating material having heat resistance is disposed in the inner layer (as shown in FIG. 1(B)). Although the above wiring layer is formed on both sides of the insulating substrate 1 and the thermoplastic base material 5, it may be formed on both sides of the dielectric film 9. Alternatively, holes may be provided in the dielectric film 9 in advance and processed so that the dielectric sheets can be sandwiched and connected to each other. Next, the pieces obtained as described above are heat-pressed by a hot press.

■次いで、単位配線シート8と誘電体フィルム9を複数
枚積層した状態で熱プレスにより加熱圧着し、内部に誘
電体フィルム10.上部電極4及び下部電極7から構成
されるコンデンサlOを内蔵した多層配線回路モジュー
ルを製造する(第1図(C)図示)。上記熱プレスの温
度、圧力、加圧時間等は、使用した材料により異なり、
その条件は適宜選択する。なお、上述した一体化により
、スルホール内の電気的接続を含めて最終的な導体パタ
ーンが同時に形成される。また、前記導体ペーストは熱
可塑性樹脂でできているため、加熱圧着により上下の単
位配線シート上の導体パターン同士が加熱融着され、電
気的コンタクトが確実に行われる。更に、コンデンサ用
の強誘電体フィルムに単位配線シートよりも熱変形温度
が高い基材を用いれば、加熱圧着の際に該コンデンサ用
の強誘電体フィルムが熱変形を生じずに初期の誘電体特
性を維持できる。
(2) Next, a plurality of unit wiring sheets 8 and dielectric films 9 are laminated and bonded under heat using a heat press, and a dielectric film 10. A multilayer wiring circuit module containing a built-in capacitor 1O composed of an upper electrode 4 and a lower electrode 7 is manufactured (as shown in FIG. 1(C)). The temperature, pressure, pressing time, etc. of the above heat press vary depending on the material used.
The conditions are selected as appropriate. Note that by the above-described integration, the final conductive pattern including the electrical connections within the through holes is formed at the same time. Furthermore, since the conductor paste is made of thermoplastic resin, the conductor patterns on the upper and lower unit wiring sheets are thermally fused together by heat-pressing, thereby ensuring electrical contact. Furthermore, if a base material with a higher thermal deformation temperature than that of the unit wiring sheet is used for the ferroelectric film for capacitors, the ferroelectric film for capacitors will not undergo thermal deformation during hot press bonding and will maintain its original dielectric state. Characteristics can be maintained.

このようにして得られるモジュールにおいて、コンデン
サ10の静電容量Cは、誘電体フィルムの厚みをd、上
部電極と下部電極の接触面積をSとした時、C−ε−S
/dで表わされる(但し、εは有機フィルムの誘電率を
示す)。ここで、εは通常2〜5であるため、Cを大き
くするためにはフィルムの厚みdをできるだけ薄くして
多層化するか、面積Sを大きくしなければならない。し
かるに、無機質の誘電体フィルムは有機質のそれに比べ
て誘電率が非常に高く、と−5〜500程度である。従
って、従来の有機質のみの誘電体フィルムのコンデンサ
に比較して、同じd、Sの条件で大容量コンデンサを形
成する事が可能となる。
In the module obtained in this way, the capacitance C of the capacitor 10 is C-ε-S, where d is the thickness of the dielectric film, and S is the contact area between the upper and lower electrodes.
/d (where ε indicates the dielectric constant of the organic film). Here, since ε is usually 2 to 5, in order to increase C, the thickness d of the film must be made as thin as possible to form a multilayer film, or the area S must be increased. However, inorganic dielectric films have a much higher dielectric constant than organic dielectric films, about -5 to 500. Therefore, it is possible to form a large capacitance capacitor under the same d and S conditions as compared to a conventional capacitor using a dielectric film made only of organic materials.

(実施例) 以下、本発明の一実施例について製造方法を併記しつつ
説明する。
(Example) Hereinafter, an example of the present invention will be described along with a manufacturing method.

まず、熱可塑性絶縁基板として厚さ100μm1外形5
0〜60ma+のポリカーボネートのシートを用意し、
基板の所定の位置に0.5a+mφのスルホールを形成
した。次に、前記基板の一方の主面上にバインダとして
のポリ塩化ビニルを用いて、銀粉と溶剤とを以下の組成
で混練り調整した導体ペーストを印刷した。
First, a thermoplastic insulating substrate with a thickness of 100 μm and an outer diameter of 5
Prepare a polycarbonate sheet of 0 to 60 ma+,
A through hole of 0.5a+mφ was formed at a predetermined position on the substrate. Next, a conductive paste prepared by kneading silver powder and a solvent with the following composition was printed on one main surface of the substrate using polyvinyl chloride as a binder.

1、塩化ビニル−酢酸ビニルコーポリマー(酢酸ビニル
比20%)           10重量部2、銀粉
(粒径3μm)90重量部 3、溶剤(シクロヘキサン、ブチルカルピトールの混合
溶剤)90重量部 次に、80℃、20分間乾燥させ印刷された導体ペース
トの溶剤を除去し、基材の他方の面に同じ導体ペースト
を印刷し、バターニングして5 X 5 l1m。
1. Vinyl chloride-vinyl acetate copolymer (vinyl acetate ratio 20%) 10 parts by weight 2. Silver powder (particle size 3 μm) 90 parts by weight 3. Solvent (mixed solvent of cyclohexane and butylcarpitol) 90 parts by weight Next, 80 parts by weight ℃ for 20 minutes to remove the solvent of the printed conductor paste, print the same conductor paste on the other side of the substrate, and pattern it to a size of 5 x 5 l1m.

10X 10a+m、 20X 20同の上部電極を形
成した。
Upper electrodes of 10×10a+m and 20×20 were formed.

次いで、誘電体フィルムとして、透孔を施した厚さ25
μmのPPS (ポリフェニレンサルファイド、県別化
学(製)の商品名KPS)フィルムを用意した。ひきつ
づき、前記基板上に前述した導体ペーストを用いて40
850a+mの下部電極を印刷形成した。
Next, as a dielectric film, a film with a thickness of 25 mm with through holes was formed.
A PPS (polyphenylene sulfide, trade name KPS, manufactured by Kenbetsu Kagaku Co., Ltd.) film of μm was prepared. Subsequently, the above-mentioned conductive paste is applied to the substrate for 40 minutes.
A lower electrode of 850a+m was formed by printing.

次に、3枚の単位配線シートを第1図(B)に示す如く
積層し、卓上型熱プレスを用いてヒータ温度150℃、
樹脂20K g / 0m2.保持時間5分として熱圧
着を行った後、直ちに冷却して取り出した。
Next, three unit wiring sheets were stacked as shown in Figure 1 (B), and a heater temperature of 150°C was set using a tabletop heat press.
Resin 20K g/0m2. After thermocompression bonding was carried out with a holding time of 5 minutes, it was immediately cooled and taken out.

しかして、上述のようにして製造される多層配線回路モ
ジュールは、誘電体フィルム9.上部電極4及び下部電
極7から構成されるコンデンサlOを内蔵し、前記誘電
体フィルム9が有機質のみならず該有機質の誘電率に比
べて非常に高い誘電率(ε−5〜50口)をもつ無機質
も含む構成となっているため、従来の有機質のみの誘電
体フィルムのコンデンサに比較して、同じd、Sの条件
で大容量コンデンサを形成する事ができ、安価に大容量
、小型のコンデンサを得ることができる。また、誘電体
フィルムに温度補償形(CH,RH,PRなどのマイナ
ス傾斜の温度特性)を用いる事により、回路の温度補償
も可能にできる。つまり、各種温度のコンデンサが実現
できる。更に、加熱圧着により一体形成と多層化を行う
ために、全体の厚さを非常に薄くでき、しかも層間配線
に伴うTHメツキなど複雑なプロセスを省略することが
できる。
Thus, the multilayer wiring circuit module manufactured as described above has a dielectric film 9. It has a built-in capacitor IO consisting of an upper electrode 4 and a lower electrode 7, and the dielectric film 9 has not only an organic material but also a very high dielectric constant (ε-5 to 50) compared to the dielectric constant of the organic material. Because it has a structure that also includes inorganic materials, it is possible to form a large capacity capacitor under the same d and S conditions compared to conventional dielectric film capacitors made only of organic materials, making it possible to create large capacitance and small capacitors at low cost. can be obtained. Furthermore, by using a temperature compensation type (negative slope temperature characteristics such as CH, RH, PR, etc.) for the dielectric film, temperature compensation of the circuit can be achieved. In other words, capacitors with various temperatures can be realized. Furthermore, since integral formation and multilayering are performed by heat-press bonding, the overall thickness can be made extremely thin, and complicated processes such as TH plating associated with interlayer wiring can be omitted.

小実、得られた基板の上面にはコンデンサの下部電極が
プレスにより誘電体フィルムのスルホールを通って露出
し、電気的81定が可能となっている。下記第1表は、
3つのパターンの容量をYHP製LCRメータを用いて
測定した結果を示す(但し、測定周波数1μHz)。
On the upper surface of the obtained substrate, the lower electrode of the capacitor is exposed through a through hole in the dielectric film by pressing, making it possible to maintain an electrical constant of 81°. Table 1 below is
The results of measuring the capacitance of three patterns using an LCR meter manufactured by YHP are shown (however, the measurement frequency is 1 μHz).

第1表 また、総厚は約200μmであり、スルホールを含む接
着の信頼性も一り0℃〜+GO℃、200サイクルで異
品は見られず良好であった。
Table 1 also shows that the total thickness was about 200 μm, and the reliability of adhesion including through-holes was good, with no foreign products observed at 0° C. to +GO° C. for 200 cycles.

[発明の効果] 以上詳述した如く本発明によれば、従来の有機質材II
のみによる強誘電体フィルムを用いたコンデサに比べ、
耐熱性が良くかつ誘電率の高いフィルムの形成を可能と
し、もって大容量、小型のコンデンサを形成しえる多層
配線回路モジュールを堤供できる。
[Effects of the Invention] As detailed above, according to the present invention, the conventional organic material II
Compared to capacitors using only ferroelectric film,
It is possible to form a film with good heat resistance and a high dielectric constant, thereby providing a multilayer wiring circuit module that can form a large-capacity, small-sized capacitor.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は多層配線回路モジュールを製造工程順に示す断
面図である。 1・・・熱可塑性絶縁基板、2・・・スルホール、4・
・・上部電極、5・・・配線層、6・・・熱可塑性基材
、7・・・下部電極、8・・・単位配線シート、9・・
・強誘電体フィルム、lO・・・コンデンサ。 出動人代理人 弁理士 鈴江武彦 531−
FIG. 1 is a cross-sectional view showing a multilayer wiring circuit module in the order of manufacturing steps. 1... Thermoplastic insulating substrate, 2... Through hole, 4...
... Upper electrode, 5... Wiring layer, 6... Thermoplastic base material, 7... Lower electrode, 8... Unit wiring sheet, 9...
・Ferroelectric film, lO...capacitor. Representative of dispatcher Patent attorney Takehiko Suzue 531-

Claims (1)

【特許請求の範囲】[Claims] 熱可塑性絶縁基板と、この絶縁基板の少なくとも片面側
に一体的に設けられ、主面に配線パターンを形成した複
数の単位配線シートと、前記絶縁基板とシート間または
シート同士間に設けられ、高誘電率を有する微細粉末材
料及び耐熱性を有する有機高分子絶縁材料を混練りしシ
ート状にしてなる強誘電体フィルムと、この強誘電体フ
ィルムの少なくとも片面に形成された電極とを具備した
ことを特徴とする多層配線回路モジュール。
A thermoplastic insulating substrate, a plurality of unit wiring sheets integrally provided on at least one side of the insulating substrate and having a wiring pattern formed on the main surface, and a plurality of unit wiring sheets provided between the insulating substrate and the sheets or between the sheets, and having a high A ferroelectric film formed into a sheet by kneading a fine powder material having a dielectric constant and an organic polymer insulating material having heat resistance, and an electrode formed on at least one side of the ferroelectric film. A multilayer wiring circuit module featuring:
JP1343629A 1989-12-28 1989-12-28 Multilayer wiring circuit module Pending JPH03201593A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1343629A JPH03201593A (en) 1989-12-28 1989-12-28 Multilayer wiring circuit module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1343629A JPH03201593A (en) 1989-12-28 1989-12-28 Multilayer wiring circuit module

Publications (1)

Publication Number Publication Date
JPH03201593A true JPH03201593A (en) 1991-09-03

Family

ID=18363008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1343629A Pending JPH03201593A (en) 1989-12-28 1989-12-28 Multilayer wiring circuit module

Country Status (1)

Country Link
JP (1) JPH03201593A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7173842B2 (en) * 2004-03-31 2007-02-06 Intel Corporation Metal heater for in situ heating and crystallization of ferroelectric polymer memory film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7173842B2 (en) * 2004-03-31 2007-02-06 Intel Corporation Metal heater for in situ heating and crystallization of ferroelectric polymer memory film

Similar Documents

Publication Publication Date Title
TWI299900B (en) Printed circuit board having embedded capacitors using hybrid material and method of manufacturing the same
TWI277375B (en) Co-fired ceramic capacitor and method for forming ceramic capacitors or use in printed wiring boards
JPH0648666B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
US4835656A (en) Multi-layered ceramic capacitor
JP3956851B2 (en) Passive element embedded substrate and manufacturing method thereof
JPS60137092A (en) Circuit board
KR20090083568A (en) Printed circuit board with embeded capacitor and fabricating method thereof
KR100972874B1 (en) Itfc with optimized ct
JP3199664B2 (en) Method for manufacturing multilayer wiring board
JP3944791B2 (en) Ceramic multilayer printed circuit board
JP4207517B2 (en) Embedded substrate
JP2006510233A (en) Printed wiring board having low-inductance embedded capacitor and manufacturing method thereof
JPS60249386A (en) Functional substrate and electronic circuit substrate using same
JPS63300593A (en) Ceramic composite substrate
JPH03201593A (en) Multilayer wiring circuit module
JPS5917232A (en) Composite laminated ceramic part and method of producing same
JPS62210693A (en) Circuit module with built-in capacitor
JP2004172530A (en) Laminated dielectric sheet, and capacitor sheet integrated into board, and element integrating board
JPS6092697A (en) Composite laminated ceramic part
JPS59132643A (en) Resistor composite substrate
JPH0216004B2 (en)
JPS6088420A (en) Composite laminated ceramic part
JPH0515292B2 (en)
JPS5917294A (en) Composite laminated ceramic part and method of producing same
JPH022318B2 (en)