JP2004172530A - Laminated dielectric sheet, and capacitor sheet integrated into board, and element integrating board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor sheet integrated into a board wherein a thin large electrostatic capacity can be obtained and the capacity can be altered easily; to provide an element integrating board integrating the capacitor sheet thereinto. <P>SOLUTION: In the capacitor sheet, there are used a plurality of laminated dielectric sheets on a single surface of each of which a plurality of blocked inner-layer electrodes are formed and wherein the inner-layer electrode of each dielectric sheet has the portions overlapping with no inner-layer electrodes of its upper-side and lower-side dielectric sheets. Further, in the capacitor sheet, the electric connections among its outermost-layer electrodes and its inner-layer electrodes are performed by through holes similarly to the manufacturing process of a general printed wiring board. The design of the electrostatic capacity of a capacitor element using this capacitor sheet can be altered easily. Also, when these capacitor sheets are laminated as the capacitor layer of a general printed wiring board, the plurality of capacitor elements can be so integrated at the same time into the printed wiring board as to make obtainable a high-performance thin board integrating the elements thereinto. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a module with a built-in passive element, such as a capacitor element, and a substrate with a built-in passive element, in which the passive element is disposed inside an electrically insulating substrate.
[0002]
[Prior art]
In recent years, with the demand for higher performance, smaller size, and higher frequency of electronic devices, there is a demand for higher density and higher functionality of semiconductors. For this reason, in addition to the semiconductor, passive components such as a capacitor (C), an inductor (L), and a resistor (R) are also miniaturized, and a circuit board for mounting chip passive components with guaranteed characteristics. However, there is a need for a smaller and higher density.
[0003]
In response to these requirements, for example, an inner via hole (hereinafter referred to as IVH) connection method, which is an electrical connection method between substrate layers that can connect electrical wiring between LSIs and mounted components at the shortest distance, has the highest circuit. Development is being promoted in various directions because of the possibility of high density wiring. In general, examples of the wiring board having such an IVH configuration include a multilayer ceramic wiring board, a multilayer printed wiring board by a build-up method, and a multilayer composite wiring board made of a mixture of a resin and an inorganic filler.
[0004]
The multilayer ceramic wiring board can be manufactured as follows, for example. First, prepare a plurality of green sheets made of ceramic powder such as alumina, organic binder and plasticizer, provide via holes in each green sheet, fill the via holes with conductive paste, and then print a wiring pattern on the green sheets The green sheets are stacked. Then, the multilayer ceramic wiring board can be produced by removing the binder and firing the laminate. Since such a multilayer ceramic wiring board has an IVH structure, an extremely high density wiring pattern can be formed, which is optimal for downsizing of electronic devices.
[0005]
Also, printed wiring boards based on the build-up method that mimic the structure of this multilayer ceramic wiring board have been developed in various fields. For example, in JP-A-9-116267 and JP-A-9-511168, as a general build-up method, a conventionally used glass-epoxy substrate is used as a core, and photosensitive insulation is provided on the surface of the substrate. A method is disclosed in which after forming a layer, via holes are formed by photolithography, copper plating is further performed on the entire surface, and the copper plating is chemically etched to form a wiring pattern.
[0006]
Japanese Patent Laid-Open No. 9-326562 discloses a method of filling a via hole processed by the photolithography method with a conductive paste as in the build-up method. In Kaihei 10-51139, etc., a conductive circuit is formed on one surface of an insulating hard substrate, an adhesive layer is formed on the other surface, a through hole is provided in this, and a conductive paste is filled. A multilayering method in which a plurality of base materials are stacked and stacked is disclosed.
[0007]
Patent Nos. 2601128, 2603305, and 2587596 are provided with through holes in an aramid-epoxy prepreg by laser processing, filled with a conductive paste, and then laminated with copper foil and patterned. In this method, the substrate is used as a core and further sandwiched between prepregs filled with a conductive paste to form a multilayer.
[0008]
As described above, for example, if the resin-based printed wiring board is IVH-connected, it is possible to electrically connect only the necessary layers as in the multilayer ceramic wiring board. Since there is no through hole, it is more excellent in mountability.
[0009]
However, as described above, even in a multilayer wiring board with high density wiring, the proportion of electronic components mounted on the surface of the wiring board, such as capacitors and resistors, is still high, which is a major factor for downsizing electronic devices. It has become a challenge. As a solution to such a problem, a proposal for embedding electronic components in a wiring board to achieve high-density mounting has been disclosed.
[0010]
For example, a configuration in which a leadless part is embedded in a through hole provided in a printed circuit board is disclosed in Japanese Patent Laid-Open No. 54-38561, and a configuration in which a passive element such as a ceramic capacitor is embedded in a through hole provided in an insulating substrate. Japanese Laid-Open Patent Publication No. 60-41480 and a configuration in which a bypass capacitor of a semiconductor element is embedded in a hole of a printed wiring board are disclosed in Japanese Patent Application Laid-Open No. Hei 4-73992 and Patent Document 1.
[0011]
In addition, Patent Document 2 in which a conductive material and a dielectric material are filled in a via hole (IVH) provided in a ceramic wiring substrate and simultaneously fired, after an electronic component forming material is embedded in a through hole provided in an organic insulating substrate A configuration in which a capacitor and a resistor are formed by solidification is disclosed in Patent Document 3 and the like.
[0012]
Any of the above conventional disclosed techniques can be roughly divided into two systems. That is, one of them is to bury embedded leadless parts such as chip resistors or chip capacitors in through holes provided in the wiring board, and then to conduct the leads and the wiring pattern on the wiring board. The connection is made by paint or soldering. In addition, in the case of an organic wiring board, an electronic component forming material such as a capacitor is embedded in a through hole provided in the wiring board and solidified to obtain a desired capacitor, and then the upper and lower end surfaces thereof are plated. To form an electronic component built-in wiring board, and in the case of an inorganic wiring board, after filling a dielectric paste or conductive paste in a via hole (IVH) provided in a ceramic green sheet, By baking at a high temperature, a wiring board having a desired capacitor is formed.
In addition, a through-hole here means the hole which penetrates one of the layers which comprise a printed wiring board.
[0013]
However, it is difficult to obtain a large capacity with a capacitor fired or solidified using these through holes. On the other hand, when embedding and mounting a chip capacitor or the like having a large capacity in advance using a through hole, a layer thickness of 0.6 mm is always accompanied even when using the current, minimum size 0603 chip, It becomes difficult to realize a thin multilayer substrate.
[0014]
Further, when viewed as a single chip component, in the market, a chip component in which an electrode is formed on a side surface represented by 1005, 0603 is typical, and an example in which these are built in a substrate is disclosed in Patent Document 4 (US Patent). No. 6,038,133) has already been proposed, but a structure in which the structure and the shape are taken into consideration for the built-in and the form in which it is built in the substrate is still proposed. Not. Furthermore, when viewed as a single chip component, there are single-layer chip capacitors and thin-film multilayer capacitors as elements having electrodes on the top and bottom surfaces, but these are only supposed to be surface-mounted, and there is a wire between the electrodes. It is generally used to connect with a bond or with a ribbon lead. Therefore, there has not yet been proposed an effective manufacturing method for incorporating these chip components in a substrate and connecting them with a wiring pattern with high accuracy.
[0015]
On the other hand, a structure in which a dielectric layer is provided on the entire surface of an inner layer of a multilayer printed wiring board using a dielectric layer sheet having both sides sandwiched between copper foils (Patent Document 5, Patent Document 6, and Patent Document 7) Proposed. Since the structure of this structure is a single layer, the electrostatic capacity per unit area is extremely low compared to a chip component, but the required capacity can be obtained by increasing the electrode area. Further, unlike the above-described chip component embedding type, it is advantageous in manufacturing because a lamination process for manufacturing a multilayer printed board can be used. As a disadvantage, a sintered ceramic dielectric material cannot be used because it is built in the substrate with a large area. In other words, a material in which a dielectric filler is kneaded with resin must be used, and the dielectric constant of the material is two or more orders of magnitude lower than that of inorganic materials, and the area of one capacitor per unit capacity becomes enormous, making the substrate smaller. The problem is that it is impossible to embed a plurality of capacitors. Furthermore, the capacitance of the capacitor can be changed by the dielectric constant of the dielectric layer, the distance between the electrodes and the area, but in this structure, it can only be changed by the area, so it is practically difficult to incorporate capacitors with different capacities. It was a problem.
[0016]
[Patent Document 1]
JP-A-5-218615 (2nd page, paragraph 7)
[Patent Document 2]
JP-A-8-222656 (page 3, paragraphs 11-14)
[Patent Document 3]
JP-A-10-56251 (page 3, paragraphs 7-8)
[Patent Document 4]
JP-A-11-220262 (pages 7-8, paragraphs 42-54)
[Patent Document 5]
US Pat. No. 5,079,069
[Patent Document 6]
US Pat. No. 5,155,655
[Patent Document 7]
U.S. Pat.
[0017]
[Problems to be solved by the invention]
FIG. 1 is a schematic partial sectional view of a conventional planar type capacitor element built-in substrate. A so-called planar type capacitor element (101) in which a dielectric layer (106) in which a conventional dielectric filler is kneaded with a binder resin is provided on the entire surface of the substrate and electrode patterns (102) are provided on the upper and lower sides has a small capacitance. Was a problem. In addition, multilayer ceramic chip capacitors used for surface mounting are not manufactured for the purpose of being embedded in a substrate, so that although they are small, the thickness is inappropriate, and the shape of the terminal electrode of the capacitor element is also unsuitable for incorporation. It was.
[0018]
The present invention secures a necessary capacitance for use in a device-embedded substrate, provides a capacitor device having an optimum structure in consideration of the manufacturing process of a multilayer printed wiring board, and has excellent embedded reliability that has not been obtained in the past. An element-embedded substrate is provided.
That is, the present invention has been devised in view of the above-described problems, and a plurality of capacitor elements can be mounted with a single capacitor layer when a chip component is built in a substrate, and the capacitance of each capacitor element can be adjusted as necessary. Capacitor element layer for element built-in substrate that can be freely changed from low capacity to large capacity, and chip passive components such as LCR while forming connection with wiring pattern while forming fine wiring pattern on circuit board It is an object of the present invention to provide a method of manufacturing an element-embedded substrate that is accurately mounted and embedded.
[0019]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the first invention according to claim 1 is a dielectric in which a plurality of inner layer electrodes are formed on the same surface of a plurality of dielectric sheets. A dielectric laminated sheet for a capacitor element with a built-in substrate, characterized in that a plurality of sheets are laminated such that the plurality of dielectric sheets have portions where inner layer electrodes on each dielectric sheet do not overlap with upper and lower inner layer electrodes. is there.
[0020]
According to a second aspect of the present invention, the thickness of one layer of the dielectric sheet is 5 to 100 μm or less, and the thickness of the dielectric laminated sheet for a substrate built-in capacitor element is 10 to 600 μm or less. The dielectric laminated sheet for a capacitor element with a built-in substrate according to claim 1.
[0021]
A third invention according to claim 3 is characterized in that the dielectric sheet includes at least a thermoplastic resin and / or a thermosetting resin, and a dielectric filler. It is a dielectric laminated sheet for elements.
[0022]
According to a fourth aspect of the present invention, the dielectric filler includes:
BaTiO₃, SrTiO₃, CaTiO₃, Mg₂TiO₃ZnTiO₃, La₂Ti₂O₇, Nd₂Ti₂O₇, PbTiO₃, CaZrO₃, BaZrO₃, PbZrO₃, BaTi_1-xZr_xO₃, PbZr_xTi_1-xO₃
(0 ≦ x ≦ 1)
4. The dielectric laminated sheet for a capacitor element with a built-in substrate according to claim 3, wherein the dielectric laminated sheet is one or more selected from the group consisting of:
[0023]
According to a fifth aspect of the present invention, a plurality of electrodes are provided on the outermost layer of the dielectric laminated sheet according to any one of the first to fourth aspects, and the inner layer electrode in the dielectric laminated sheet is either upper or lower A capacitor sheet with a built-in substrate, wherein the capacitor element is formed by being electrically connected to an outermost electrode.
[0024]
According to a sixth aspect of the present invention, the area of the outermost layer electrode in the capacitor element is equal to or larger than the area of one inner layer electrode in the capacitor element. It is a sheet.
[0025]
A seventh invention according to claim 7 is a capacitor sheet with a built-in substrate, wherein the inner layer electrodes according to claim 5 or 6 are electrically connected on the same plane.
[0026]
The eighth invention according to claim 8 is characterized in that the capacitance of the capacitor element is adjusted by not taking a part of the electrical connection between the upper and lower inner layer electrodes constituting one capacitor element. To a capacitor sheet with a built-in substrate according to any one of 1 to 7.
[0027]
A ninth invention according to claim 9 is the capacitor sheet with a built-in substrate according to any one of claims 5 to 8, wherein the outermost layer electrode is a copper foil.
[0028]
According to a tenth aspect of the present invention, there is provided an element-embedded substrate in which a capacitor layer is formed by stacking the capacitor sheets according to any one of the fifth to ninth aspects.
[0029]
An eleventh invention according to an eleventh aspect is the device-embedded substrate according to the tenth aspect, in which the capacitor sheet according to any one of the fifth to ninth aspects is coated with an insulating material and then a wiring pattern is provided. is there.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
The present invention is a multilayer printed wiring board (element-embedded substrate) having one or more insulating layers, wherein at least one capacitor layer is laminated on at least an inner layer, and at least two capacitor layers are provided on the capacitor layer. The capacitor layer has a structure in which a plurality of inner layer electrodes and a plurality of dielectric layers are alternately stacked. In addition, the capacitor element of the capacitor layer can adjust the capacitance by electrically connecting the inner layer electrodes provided in advance and changing the electrode area of the upper and lower outermost layers. Can be obtained.
[0031]
When a normal multilayer capacitor is manufactured, the pattern shape of the inner layer electrode needs to be provided in advance in an area that matches the required capacity, and the capacitance is fixed by the shape of the inner layer electrode. However, in the present invention, the inner layer electrodes are divided into a plurality of parts and electrically connected in a necessary number, thereby enabling various combinations of electrode areas. The inner layer electrode can be connected in the vertical direction with vias, and the left and right connections can be made by making the outermost layer electrode larger, using a conductive paste, or providing a wiring pattern. According to this method, it is possible to obtain a low-capacitance capacitor element by extending the distance between the electrodes by not providing a part of the conduction of the plurality of electrodes in the inner layer. The present invention provides a capacitor layer capable of simultaneously incorporating a plurality of capacitors having various capacitances adjusted in a single layer, and an element-embedded substrate provided with the capacitor layer.
[0032]
In other words, the capacitance of the element that could not be achieved with a single layer is secured by expanding the electrode area and multilayering, and in order to incorporate a plurality of capacitor elements in the same layer, it is necessary to preliminarily form the inner dielectric layer. A plurality of inner layer electrodes are provided, and the upper and lower layers of these inner layer electrodes are electrically connected by through holes and combined with the shape of the upper and lower outermost layer electrodes to incorporate a plurality of elements having various electrostatic capacities. It is what makes it possible. Further, a resin material is used for the dielectric layer so as to be suitable for incorporation in a multilayer printed wiring board.
[0033]
The dielectric laminated sheet (303) described in the present invention is formed by sequentially laminating dielectric layers and electrodes. An example of the manufacturing process is shown in FIGS. The dielectric layer (201) is preferably a thermoplastic resin, a thermosetting resin, or a mixture of them and a dielectric filler kneaded (FIG. 2 (a)). The reason for this is that, for example, using a ceramic fired into a sheet can increase the dielectric constant and increase the electrostatic capacity, but if it is thinned, it is prone to cracking and may not function due to cracks in the multilayer printed wiring board manufacturing process. It is. In contrast, a resin material has a low dielectric constant but has a certain degree of flexibility, and is therefore suitable for a device-embedded substrate.
[0034]
In the present invention, polyester, polyimide, polyamide, polyamideimide, polyethersulfone, polysulfone, polyetheretherketone, polystyrene, polyethylene, polypropylene, or the like can be used as the thermoplastic resin.
In the present invention, a three-dimensional cured product such as an epoxy resin, a phenol resin, a urethane resin, a melamine resin, or an acrylic resin can be used as the thermosetting resin.
[0035]
In the present invention, a dielectric filler is kneaded with the above-described thermoplastic resin, thermosetting resin, or mixture thereof and used as a dielectric layer. At this time, additives such as a solvent, a dispersant, and a coupling agent may be used as necessary. When a thermosetting resin is contained as a component, it is used after being thermally cured by heating after the formation of the dielectric layer.
[0036]
In the present invention, BaTiO is used as a dielectric filler.₃, SrTiO₃, CaTiO₃, Mg₂TiO₃ZnTiO₃, La₂Ti₂O₇, Nd₂Ti₂O₇, PbTiO₃, CaZrO₃, BaZrO₃, PbZrO₃, BaTi_1-xZr_xO₃, PbZr_xTi_1-xO₃(0 ≦ x ≦ 1) or the like can be used, and these may be used alone or in combination as necessary.
The ratio of the resin and dielectric filler of the dielectric layer described in the present invention can be changed depending on the required capacity of the capacitor element. Therefore, although not particularly limited, in order to obtain a high capacity, it is usually desirable to add a dielectric filler of 50 wt% or more.
[0037]
The inner layer electrode (202) used for the capacitor element described in the present invention is not particularly limited as long as it is a conductive material, and is a metal foil or a conductive paste in which conductive fine particles such as carbon and metal fine particles are kneaded into a resin. Can be used. As shown in FIG. 2B, a plurality of inner layer electrodes that can be combined are provided in advance on the dielectric layer by screen printing or the like.
[0038]
As a method of manufacturing the capacitor element described in the present invention, a dielectric sheet or a sheet-like dielectric made of a resin kneaded with a filler is prepared in advance, and is sandwiched and etched by a conductor such as a copper foil to form an inner electrode pattern. After forming or printing the inner layer electrode pattern with a conductive paste on a sheet-like dielectric, the following dielectric layers are sequentially stacked. At this time, in order to increase the adhesion between the dielectric layers and the electrodes, it is desirable to press under heat and pressure as necessary. Further, when an uncured thermosetting resin is included as a component, it is cured by heating in the lamination process, or is used by being thermally cured after being built in a printed circuit board. Finally, a dielectric laminated sheet for a capacitor element with a built-in substrate having a structure in which a conductor layer serving as an electrode is disposed on the outermost layer (FIG. 3).
[0039]
The electrode shape of each layer of the capacitor element described in the present invention has a special pattern for varying an arbitrary capacitance at the connection position. An example is shown in FIG. FIG. 4A shows an example of the shape of the first inner electrode pattern (301-1) of the dielectric laminated sheet shown in FIG. Similarly, FIG. 4B shows the inner electrode pattern (301-2) of the second layer in the dielectric laminated sheet shown in FIG. 3, and FIG. 4C shows the third layer of the dielectric laminated sheet shown in FIG. The inner layer electrode pattern (301-3) is shown. The conductor layer 302 in FIG. 3 is preferably a copper foil because it is easy to handle, and can be etched into an arbitrary shape to form the outermost electrode (501) shown in FIG. The overlapping portion of the outermost layer electrode (501) and the upper and lower inner layer electrodes (301-1 to 301-3) functions as a capacitor layer to constitute a capacitor element.
[0040]
In the example shown here, eight positions from (a) to (h) shown in FIG. 4 (d) can be selected as the formation positions of the through holes that electrically connect the electrodes, and these are combined to form a capacitor. The capacitance of the element can be adjusted. When the interlayer capacitance of all layers is used, the capacitance of the capacitor element of the present invention is maximized, while the inner layer electrode (202) is not electrically connected, and only the outermost layer electrodes (501) are connected. In the structure, the electrostatic capacity is minimized. That is, theoretically, the minimum value and the maximum value of the capacitance can be changed in the range of the square of the number of dielectric layers. Furthermore, it is possible to obtain a larger capacitance by electrically connecting and combining adjacent electrodes. For this reason, a great degree of freedom is obtained in terms of circuit design and production efficiency, which is very advantageous.
[0041]
5A and 5B show examples of the electrode structure on the front and back of the dielectric laminated sheet (303). By patterning the copper foil as the conductor layer (302) on the front and back sides as shown in FIGS. 5 (a) (501-F) and (b) (501-B) to form the outermost electrode (501). A capacitor sheet (601) shown in FIG. 6 (a) is obtained.
[0042]
The capacitor sheet and capacitor element of the present invention have at least two or more dielectric layers (201). Therefore, the electrodes sandwiching the dielectric layers are three layers including the inner layer electrode (202) and the outermost layer electrode (501). It shall have the above. It is desirable to have three or more dielectric layers. This is because the dielectric constant of the resin-based dielectric layer has a low dielectric constant, and in order to obtain the required capacitance of the capacitor element with only one layer, the area must be large, and there is a restriction on the capacity and the number of capacitors that can be embedded. To receive. Capacitor capacity can be increased by using a multilayer structure. Further, the thickness of the dielectric layer (201) of the capacitor element of the present invention is preferably 100 μm or less per layer, and more preferably 50 μm or less. The reason for this is that the thinner the capacitor sheet (601) itself is, the easier it is to embed it in the printed wiring board, and the capacitance is inversely proportional to the distance between the electrodes. This is because it can be done.
[0043]
The outermost layer electrode (501) and the inner layer electrode (202 or 301-1 to 301-3) of the capacitor element of the present invention have through-holes at any predetermined positions shown in FIGS. After opening (502) (FIG. 6 (b)), conduction between the upper and lower sides is obtained by embedding the conductive paste (602) or plating the inside of the through hole with metal (FIG. 6 (c)). As a method of opening the through hole (502), a drill method, a punch method, a pin insertion method, laser processing, or the like can be performed. In this way, a capacitor sheet (603) in which electrical connection is made between the inner layer electrodes is obtained.
[0044]
The thickness of the capacitor sheet (601) described in the present invention is preferably 600 μm or less, and particularly preferably 500 μm or less. This is because when the element is built in the printed circuit board, if the thickness is larger than this, the entire printed circuit board becomes too thick due to the capacitor sheet.
[0045]
As a method for manufacturing an element-embedded substrate using the capacitor sheet of the present invention, a conductor layer (703) is laminated via a prepreg which is an insulating material (702) in the same process as a normal multilayer printed wiring board, and wiring is performed. A method of forming a pattern (FIG. 7), laminating a resin insulating sheet used for forming a built-up layer instead of using a prepreg, or a method of incorporating a multilayer structure by a built-up method using a resin varnish, etc. can give.
[0046]
Since the capacitor sheet of the present invention is very thin and compact, a plurality of layers can be laminated in the same printed wiring board.
In addition to the capacitor sheet, the element-embedded substrate of the present invention may be used by embedding a resistor element or an inductor element in the capacitor layer or in another layer.
The element-embedded substrate of the present invention can be used by providing various surface mount components such as a chip capacitor, a resistor, and an IC on the substrate in the same manner as a normal printed wiring board.
[0047]
【Example】
(Example 1)
An embodiment of the present invention will be described with reference to the drawings.
The configuration of the dielectric sheet (203) is shown in FIG. 20 parts by weight of polyethersulfone (manufactured by Sumitomo Chemical Co., Ltd .: trade name Sumika Excel 5003P) as a thermoplastic binder resin, and 80 parts by weight of barium titanate (manufactured by Sakai Chemical Industry Co., Ltd .: trade name BT05) as a high dielectric filler -After sufficiently dispersing using a mixed solvent of butyrolactone and N-methylpyrrolidone, coating with a coater on a polyimide sheet as a support, drying to remove the solvent, a dielectric having a thickness of about 20 μm A sheet was obtained. Next, a section of inner layer electrode is 1 cm thick with conductive paste.²The inner layer electrode (202) is formed by a screen printing method using a screen plate in which inner layer electrode patterns of a total of 20 sections of 4 rows × 5 columns are disposed, and then the polyimide sheet of the support is peeled off to form a dielectric. A sheet (203) was obtained. (FIG. 2 (a), (b)).
In Example 1, a total of three dielectric sheets were produced. At this time, the inner layer electrode pattern of the first layer is produced using a screen plate in which the inner layer electrode pattern (301-1) shown in FIG. 4A is arranged in a total of 20 sections of 4 rows × 5 columns. The inner layer electrode pattern (301-2) shown in FIG. 4B was used for the eyes, and the inner electrode pattern (301-3) shown in FIG. 4C was used for the third layer.
[0048]
Next, the upper and lower inner electrode (202) of each dielectric sheet is 1 cm.²3 sheets of dielectric sheets are stacked so as to overlap with each other, and finally a sheet-like dielectric on which no electrode is printed is stacked as a fourth dielectric layer, and then a conductive layer (302) is formed on both front and back sides. A surface-roughened copper foil having a thickness of 8 μm was hot-pressed at about 280 ° C. (FIG. 3).
[0049]
In the case of the present embodiment, since the wiring is provided as a through hole formation planned position in advance at a position where the inner layer electrodes can be electrically connected to each other through the through hole, dielectric sheets may be laminated so that the inner layer electrodes themselves overlap. Absent. When the shape of the inner layer electrode is a simple rectangular pattern or the like (for example, FIG. 2B), the dielectric sheets are stacked so that the upper and lower inner layer electrodes are alternately shifted and overlapped to form a through hole. At this time, it is arranged so that all inner layer electrodes constituting one capacitor element are not connected by one through hole.
[0050]
Thereafter, the copper foil on the front surface is patterned by etching as shown in FIGS. 5 (a) and (501-F), and the copper foil on the back surface is etched as shown in FIGS. 5 (b) and (501-B) to form the outermost electrode (501). Formed (FIG. 6A). At this time, the formation positions of the through holes (502) are 1st, 2nd, 3rd, 4th, all 5th, 3rd, 5th, and 4th rows, In the second position, the fifth column and the second row are positioned so as to be connected to the second position, and the position of the electrode pad of the through hole is provided (see FIGS. 2B and 5).
[0051]
When the through hole (502) is formed at the position of h and h, the outermost electrode layer and the second inner layer electrode are connected by the through hole at the position of h, and the first layer is formed by the through hole at the position of h. And the inner electrode of the third layer are connected.
In the case of forming at the positions of A and D, only the outermost layer electrode (501-F) shown in FIG. 5A is connected by the through hole at the position of A, and the second inner layer is formed by the through hole at the position of D Connect only the electrodes. At this time, the connection with the outermost layer electrode (501-B) shown in FIG.
When a through-hole is formed at the position of A and F, the outermost layer electrode (501-F) shown in FIG. 5A is used for the through-hole at the position of A, and FIG. The outermost layer electrodes (501-B) shown in FIG. At this time, connection with the inner layer electrode is not performed.
A through hole (502) was formed at a predetermined position of each electrode of the above 5 columns × 4 rows by using a drill (FIG. 6B). A capacitor sheet (603) in which the through hole (502) was filled with the conductive paste (602) and the electrical connection between the inner layer electrodes was made was produced (FIG. 6 (c)).
[0052]
On the capacitor sheet (603) shown in FIG. 6 (c), a copper foil having a thickness of 12 μm, which has been subjected to surface roughening treatment as a conductor layer (703), on a front surface and a back surface, and a thickness of 0.1 mm which is an insulating material (702). It bonded together by the vacuum hot press through the prepreg (FIG.7 (d)).
Next, via holes (704) were formed at positions where through holes (502) serving as external extraction electrodes of the capacitor element were formed by a UV-YAG laser (FIG. 7 (e)). Conductivity in the formed via hole (704) was obtained by electrolytic plating (FIG. 7 (f)), and then a necessary conductor circuit was etched to produce an element-embedded substrate (707) (FIG. 7 (g)). The external extraction electrode (706) of the capacitor element built in the substrate was formed on the surface as shown in FIG.
[0053]
When the capacitance between the external extraction electrodes (706) of the capacitor element shown in FIGS. 7 (g) and 8 was measured with an LCR meter, 44.9nF between a and b and 22.3nF between cd. , Ef was 16.7 nF, gh was 11.2 nF, i-j was 5.5 nF, kl was 2.6 nF, and mn was 1.31 nF.
[0054]
(Example 2)
A double-sided copper-clad glass epoxy substrate with an inner core thickness of 0.6 mm is used as an insulating substrate (1001), and the front and back electrodes are connected by through holes (1002) by a normal printed board manufacturing process. The core substrate (1005) in which the electrode pattern on the surface to be the outermost layer electrode (1003) at the positions indicated by 9a to l is FIG. 5 (a) (501-F) was produced (FIG. 10 (a)). .
[0055]
Next, as a thermosetting binder resin, 80 parts by weight of epoxy resin A (manufactured by Nippon Kayaku Co., Ltd .: trade name EPPN502H), 20 parts by weight of epoxy resin B (manufactured by Showa Polymer Co., Ltd .: trade name Epicoat 802), a curing agent (Arakawa) 62 parts by weight of Chemical Industries, Ltd. (trade name Tamanoru) are dissolved in a solvent (Daicel Chemical Industries, Ltd .: Trade name Metoace), and barium titanate (manufactured by Sakai Chemical Industry: trade name BT-05) is used as a high dielectric filler. After sufficiently dispersing so that the solid content ratio with the resin content (curing agent) is 80 wt%, it is coated on the core substrate 1505 using a die coater, and then dried and heated at 120 ° C. for 1 hour to about 20 μm. A dielectric layer (1006) having a thickness of 10 mm was obtained (FIG. 10B).
[0056]
On the dielectric layer (1006) thus formed, the area of the inner layer electrode of one section is 1 cm.²The inner layer electrode (the inner layer electrode (301-3) shown in FIG. 4 (c), which is the same as in Example 1, is screen-printed using a screen plate with 5 columns × 4 rows. 1007) was formed (FIG. 10C).
[0057]
A dielectric layer is formed on the inner layer electrode (1007) in the same manner as described above, and then the inner layer electrode is connected to the lower layer electrode by 1 cm.²Were sequentially provided by screen printing of a conductive paste so as to have an overlap, and four dielectric layers each having an electrode were provided (FIG. 10D). Here, the shape of the electrode (1007) on the first dielectric layer (1006) is the same as in Example 1, but the inner layer electrode pattern (301-3) shown in FIG. The inner layer electrode (1009) on the second dielectric layer (1008) has the shape of the inner layer electrode pattern (301-2) shown in FIG. The shape of the inner layer electrode (1011) on the dielectric layer (1010) is the inner layer electrode pattern (301-1) shown in FIG. 4 (a), and the outermost layer electrode on the fourth dielectric layer (1012) ( The shape of 1013) was produced using the wiring pattern (501-T) of FIG. Then, this board | substrate was heated at 180 degreeC for 1 hour, each dielectric material layer was fully hardened, and the capacitor sheet (1014) by which a dielectric material layer and an electrode were laminated | stacked alternately was obtained.
[0058]
Next, in order to electrically connect the upper and lower layer electrodes, a through-hole (502) shown in FIG. 5C is used so that the outermost layer electrodes (1003, 1013) are electrically connected to each other using a UV-YAG laser. A via hole (1015) was formed at the formation position (FIG. 10E). At this time, the electrode positions are all in the 1st, 2nd, 3rd, 4th, 5th, 3rd, 5th, and 4th rows, the 5th, 1st, 5th, 1st, 1), 2). Column 2 row is positioned so that it is connected to the position of A, and after forming a via hole (1015), the conductive paste (1016) ensures vertical conduction so as to make electrical connection, and between the inner layer electrodes A capacitor sheet (1017) to which electrical connection was made was produced (FIG. 10 (f)).
[0059]
When the through hole (502) is formed at the position of h and h, the outermost electrode 2 layers (1003 and 1013) and the second inner electrode (1009) are connected by the through hole at the position of h. The first layer (1007) and the third layer inner layer electrode (1011) are connected by the through hole at the position.
In the case of forming at positions i and d, only the outermost layer electrode (1003) is connected through the through hole at position a, and only the second inner electrode (1009) is connected through the through hole at position d. . At this time, connection with the uppermost electrode (1013) is not performed.
When forming a through-hole at positions a and f, the outermost layer electrode (1003) is connected to the through-hole at position a, and the uppermost outermost electrode (1013) is connected to the through-hole at position f. To do. At this time, connection with the inner layer electrodes (1007, 1009, 1011) is not performed.
[0060]
Next, a built-up interlayer insulating material (Ajinomoto Fine Techno Co., Ltd .: ABF-SH) having a thickness of about 50 μm was laminated as an insulating material (1102) on the front and back of the capacitor sheet (1017) using a heating vacuum press (FIG. 11 (g)).
After forming a via hole (1103) by a UV-YAG laser in order to obtain conduction of the electrode (1004) of the capacitor element provided on the core base material (1005) on the back side of the substrate (FIG. 11 (h) ) A copper layer was plated on both surfaces of the substrate to form a conductor layer (1104) (FIG. 11 (i)).
[0061]
Next, the conductive layer (1104) is etched with the wiring pattern shown in FIG. 9 so that an appropriate dummy pattern circuit is formed on the front surface and an external extraction electrode (901) is formed on the back surface at the same position as the inner electrode pattern. An element-embedded substrate was completed (FIG. 11 (j)).
[0062]
The capacitance between the external extraction electrodes (901) of the capacitor element shown in FIG. 9 and FIG. 11 (j) was measured with an LCR meter, and was found to be 43.9 nF between a and b and 22.0 nF between cd. , Ef was 16.4 nF, gh was 11.0 nF, ij was 5.5 nF, kl was 2.7 nF, and mn was 1.36 nF.
[0063]
【The invention's effect】
As described above, according to the component built-in capacitor sheet and the element built-in substrate of the present invention, it is possible to easily incorporate capacitor elements having various capacitances in the printed wiring board using a normal built-up method, The characteristics of various multilayer printed wiring boards and module substrates can be improved.
[0064]
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a conventional substrate built-in capacitor.
FIG. 2 is an explanatory view showing an example of an arrangement of a dielectric sheet constituting a capacitor sheet according to the present invention and an inner layer electrode on the dielectric layer.
FIG. 3 is a cross-sectional view of a dielectric laminate sheet constituting a capacitor sheet according to the present invention.
FIG. 4 is an explanatory view showing an example of the shape and arrangement of inner layer electrodes constituting a capacitor sheet according to the present invention.
FIG. 5 is an explanatory view showing an example of the wiring of the outermost electrode constituting the capacitor sheet according to the present invention.
(A) is the wiring diagram which looked at the capacitor sheet | seat of FIG. 6, or the core base material of Fig.10 (a) from the top.
(B) is the wiring diagram which looked at the capacitor sheet | seat of FIG. 6 from the bottom.
(C) is the wiring diagram which looked at the capacitor sheet of FIG.10 (e) from the top.
FIG. 6 is a cross-sectional view showing an example of a manufacturing process of a capacitor sheet used for an element-embedded substrate according to the present invention.
FIG. 7 is a cross-sectional view showing an example of the manufacturing process of the element-embedded substrate according to the present invention.
FIG. 8 is an explanatory diagram showing an example of the arrangement of take-out electrodes for capacitor elements built in the element-embedded substrate according to the present invention.
FIG. 9 is an explanatory view showing another example of implementation of the extraction electrode arrangement of the capacitor element built in the element built-in substrate according to the present invention.
FIG. 10 is a cross-sectional view showing another example of the manufacturing process of the capacitor sheet used for the element-embedded substrate according to the present invention.
FIG. 11 is a cross-sectional view showing another example of the manufacturing process of the element-embedded substrate according to the present invention.
[Explanation of symbols]
101 ... Planar type capacitor element
102: Wiring pattern
103 ... via hole (IVH)
104: Insulating layer
105: Dielectric layer
201: Dielectric layer
202 ... Inner layer electrode
203 ... Dielectric sheet
301-1 ... First layer inner electrode pattern
301-2 ... Inner electrode pattern of the second layer
301-3 ... Inner electrode pattern of the third layer
302 ... Conductor layer (copper foil)
303 ... Dielectric laminated sheet
401: Through-hole formation scheduled position
501: outermost electrode
501-F: outermost electrode pattern on the front side
501-B ... Electrode pattern of outermost layer on the back side
501-T: Uppermost electrode pattern on the outermost layer
502 ... through hole
503 ... Electrode pad
504 ... Wiring pattern
601. Capacitor sheet
602... Conductive paste
603. Capacitor sheet with electrical connection between inner layer electrodes
701: Capacitor layer
702 ... Insulating material (prepreg)
703 ... Conductor layer (copper foil)
704 ... via hole
705 ... Conductor layer (by plating)
706 ... External extraction electrode
707 ... Element-embedded substrate
901 ... External extraction electrode
1001 ... Insulating substrate
1002 ... Through hole
1003 ... Outermost layer electrode
1004 ... Electrode
1005 ... Core base material
1006: First dielectric layer
1007 ... 1st inner electrode
1008 ... Second dielectric layer
1009 ... Second layer inner electrode
1010: Third dielectric layer
1011 ... 3rd layer inner electrode
1012: Fourth dielectric layer
1013: outermost electrode
1014 Capacitor sheet
1015 ... via hole
1016: Conductive paste
1017: Capacitor sheet with electrical connection between inner layer electrodes
1101 ... Capacitor layer
1102 ... Insulating material
1103: Via hole
1104: Conductor layer (by plating)
1105 ... Element-embedded substrate

Claims (11)

A dielectric sheet in which a plurality of sections of inner layer electrodes are formed on the same surface of a plurality of dielectric sheets, and a portion of the plurality of dielectric sheets where the inner layer electrodes on each dielectric sheet do not overlap with upper and lower inner layer electrodes. A dielectric laminated sheet for a capacitor element with a built-in substrate, characterized in that a plurality of sheets are laminated so as to have. 2. The capacitor with a built-in substrate according to claim 1, wherein a thickness of one layer of the dielectric sheet is 5 to 100 μm or less, and a thickness of the dielectric laminated sheet for a capacitor element with a built-in substrate is 10 to 600 μm or less. Dielectric laminated sheet for device. The dielectric laminated sheet for a capacitor element with a built-in substrate according to claim 1, wherein the dielectric sheet includes at least a thermoplastic resin and / or a thermosetting resin and a dielectric filler. The dielectric filler is:
_{BaTiO 3, SrTiO 3, CaTiO 3} , Mg 2 TiO 3, ZnTiO 3, La 2 Ti 2 O 7, Nd 2 Ti 2 O 7, PbTiO 3, CaZrO 3, BaZrO 3, PbZrO 3, BaTi 1-x Zr x O ₃ , PbZr _x Ti _1-x O ₃
(0 ≦ x ≦ 1)
The dielectric laminated sheet for a capacitor element with a built-in substrate according to claim 3, wherein the dielectric laminated sheet is one type or two or more types selected from the group consisting of: A plurality of electrodes are provided on the outermost layer of the dielectric laminated sheet according to any one of claims 1 to 4, and the inner layer electrode in the dielectric laminated sheet is electrically connected to the uppermost or lowermost electrode. A capacitor sheet with a built-in substrate, wherein a capacitor element is formed. 6. The substrate built-in capacitor sheet according to claim 5, wherein an area of the outermost layer electrode in the capacitor element is equal to or larger than an area of one inner layer electrode in the capacitor element. A capacitor sheet with a built-in substrate, wherein the inner layer electrodes according to claim 5 or 6 are electrically connected on the same plane. 8. The substrate built-in capacitor according to claim 5, wherein the capacitance of the capacitor element is adjusted by not taking a part of electrical connection between upper and lower inner layer electrodes constituting one capacitor element. Sheet. 9. The substrate built-in capacitor sheet according to claim 5, wherein the outermost layer electrode is a copper foil. 10. A device-embedded substrate, wherein a capacitor layer is formed by laminating capacitor sheets according to claim 5. The element built-in substrate according to claim 10, wherein a wiring pattern is provided after the capacitor sheet according to claim 5 is coated with an insulating material.

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