JPH03198443A - Frame phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To match frame phases of respective devices connected in a multistage by outputting a synchronous frame pulse within a fixed range from the changing point of an inputted reference frame pulse and absorbing the jitter generated between the changing point of the reference frame pulse and the rising or falling point of a reference clock pulse. CONSTITUTION:Even when a reference frame pulse FP0 is inserted after or before the rise of a clock signal CK, a load pulse EG is sent 0.5-bit width of the clock pulse CK, and a frame pulse FP1 is sent within the fixed range from the change point of the reference input frame pulse FP0. Even when the reference frame pulse FP0 has jitter (deviation) to the rise of the clock signal CK, the frame pulse FP1 is stably sent. Thus, frame phases of respective devices using transmission lines connected in multistage are matched with each other.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a frame phase synchronization circuit for synchronizing the phase of signal frames between transmission devices within a station and between stations, which are separated by a large distance. The purpose is to match the frame phase of the device, and there is a phase synchronized oscillation circuit that inputs the reference frame pulse and generates the reference clock, and a phase synchronized oscillation circuit that generates the reference clock by inputting the reference frame pulse.
．． It has an edge detection circuit that generates 5 times as many pulses, and an n frequency divider that loads an initial value using the output of the edge detection circuit and performs a counting operation using the reference clock, and detects the change point of the input reference frame pulse. The synchronization frame pulse is output within a certain range width, and the jitter generated between the change point of the reference frame pulse and the rising or falling point of the reference clock pulse is absorbed.

[Industrial application field]

TECHNICAL FIELD The present invention relates to a frame phase synchronization circuit for synchronizing the phases of signal frames between transmission devices within a station and between distant stations.

The data transmitted from the transmission device on the transmitting side is multiplexed and transmitted using a signal frame synchronized with the clock signal on the transmitting side, and the signal frame received by the transmission device on the receiving side is frame synchronized with the clock signal on the receiving side. The data is sent to the receiving device. A frame phase synchronization circuit for synchronizing the received frame with the transmitted frame is provided in the transmission device on the receiving side.

(Prior Art) A block diagram of a conventional frame phase synchronization circuit is shown in FIG. 5. In the figure, 11 is a phase synchronization oscillation circuit;
A reference frame pulse from a transmission device on the transmitting side is input to generate a reference clock signal on the receiving side. Reference numeral 12 denotes a memory that stores data and reference frame pulses synchronized with the reference clock signal from the transmission device on the transmitting side, and transmits data synchronized in phase with the reference clock pulse and reference frame pulse on the receiving side to the receiving side. Reference numeral 13 denotes an n frequency divider which loads an initial value with the reference clock signal and reference frame pulses generated by the phase synchronized oscillation circuit, performs a counting operation of the reference frame pulses on the receiving side, and inserts the reference frame pulses into the memory.

In the conventional frame phase synchronization circuit, the phase synchronization oscillation circuit 1
The receiving side reference clock signal generated from 1 is divided by n frequency divider 1.
Since the frequency is simply divided by 3, the phase relationship between the reference frame pulse from the transmitting side and the output frame pulse from the receiving side is arbitrary, and the frame phases between the transmitting side device and the receiving side device are not synchronized. Not yet.

FIG. 6 shows a timing chart of the phase relationship between the input side and the output side of a conventional receiving device. In the figure, data on the input side is received at a constant cycle by a reference frame pulse FPO, and data is sent to the output side at a constant cycle by an output reference frame pulse FPI sent out from an n frequency divider. Therefore, the reference frame pulse FPO on the input side
Although the period is the same as that of the output reference frame pulse FPI, the phase relationship is arbitrary, so it is not possible to synchronize the frame phases between the devices. Therefore, the received data is stored in the memory 12 until the initialization of the reference frame pulse on the output side, increasing the amount of memory used.

[Problem to be solved by the invention]

Therefore, in conventional frame phase synchronization circuits, a delay occurs due to phase synchronization, so each device in the station requires a delay to match the input signal to its own frame phase, and the transmission path where devices are connected in multiple stages is required. There was a problem with communication using , which resulted in large signal delays. Furthermore, the capacity of the memory used in the device increases, resulting in the problem of an increase in the mounting scale of the printed circuit board.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame phase synchronization circuit with a small memory capacity that can match the frame phases of each device and minimize delays for phase synchronization.

[Means for Solving the Problems] FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 1 is a phase synchronized oscillation circuit that inputs a reference frame pulse and generates a reference clock, and 2 detects the rising or falling edge of the reference frame pulse and generates a pulse 0.5 times the reference clock bit. 3 indicates an n frequency divider which loads an initial value by the output of the edge detection circuit and performs a counting operation by a reference clock.

The n-frequency divider 3 outputs a synchronized frame pulse within a certain range from the changing point of the reference frame pulse input from the transmitting device side, and synchronizes the changing point of the reference frame pulse with the rising or falling point of the reference clock pulse. The structure is configured to absorb jitter that occurs between the two.

[Operation] FIG. 2 shows the timing chart of the frame phase synchronization circuit of the present invention. The figures show a case where a frame pulse is detected by the rising edge of a reference clock signal, and figure (a) shows a case where the frame pulse is not controlled by the reference frame pulse, and figure (b) shows a case where the frame pulse is controlled by the reference frame pulse.

In the figure, FPO is the reference frame pulse on the input side, C
K is a clock signal generated from phase synchronized oscillation circuit 1, and E is
G is the load pulse output from the edge detection circuit 2, C
OU is the count signal of n frequency divider 3, FPI is n frequency divider 3
This shows the frame pulse output from.

As shown in Figure (a), when the reference frame pulse FPO is inserted after the rising edge of the clock signal CK, the load pulse EG becomes 0 at the rising edge of the next clock signal.
．． Pulses for 5 bits are sent out, but the count value COU
starts counting from 0 without reading the load pulse EC. Therefore, the frame pulse FPI is output without receiving the control of the input frame pulse FPO.

Second, as shown in Figure (b), if the reference frame pulse FPO is inserted before the rising edge of the clock signal CK, the load pulse EG sends out a pulse equivalent to 0.5 bit in the clock signal. .

The count value COU is initialized by the load pulse EG and starts counting from 0. Therefore, the frame pulse FP receives control of the input frame pulse FPO.
I is output.

Therefore, whether the reference frame pulse FPO is inserted after or before the rising edge of the clock signal CK, the load pulse EG is sent out as a pulse with a width of 0.5 bits of the clock pulse CK, and the frame pulse FPI is It is transmitted within a certain range from the changing point of the input frame pulse FPO.

In addition, the reference frame pulse FPO is a clock (S No. CK
Even if there is jitter (deviation) with respect to the rising edge of FPI, a stable frame pulse FPI can be sent out.

(Example〕 A circuit configuration diagram of an embodiment of the present invention is shown in FIG.

In the figure, 1 is a phase synchronized oscillation circuit, 2 is an edge detection circuit, and 3 is a 1024 frequency divider.

The phase synchronized oscillator circuit 1 is an oscillator that receives a reference frame pulse FPO from the transmitting side and generates a reference clock signal CK. The edge detection circuit 2 consists of D-type flip-flop circuits 21, 22, 23, 24, an inverter circuit 25, an AND circuit 26, 27, and a NAND circuit 28.
The D-type flip-flop circuits 23 and 24 input the reference frame pulse FPO and operate in two stages in synchronization with the clock signal CK oscillated by the phase-locked oscillation circuit 1. It operates in two stages in synchronization with an inverted signal of the oscillating clock signal CK by the inverter circuit 25. The AND circuit 26 sends out a 1/2 period pulse ■ at the rising edge of the clock signal, and the AND circuit 27
sends out a 1/2 period pulse ■ at the falling edge of the clock signal. The NAND circuit 28 inputs the 1/2 period pulses ■ and ■ and sends out a negative edge detection pulse ■. 1024
The frequency divider 3 is a counter that inputs the clock signal CK and sends out a frame pulse of 171024 cycles.The frequency divider 3 inputs the edge detection pulse ■ from the edge detection circuit 2 as a load signal to initialize the counter value to 0, and then inputs it 1024 times. The frame pulse FPI is output by the counting operation.

A timing chart of the circuit operation of the embodiment is shown in FIG. Figures (a) and (b) show the case where the edge of the reference frame pulse is detected at the rising edge of the clock signal *l, *2, and Figure (C) and (d) show the case where the edge of the reference frame pulse is detected by the rising edge of the clock signal *l, *2. Falling *3. *4 indicates the case of detection, and in each case, states are shown when the reference frame signal is inserted after or before the rising or falling edge of the clock signal.

In the timing chart, ■ is a 1/2 period pulse that operates on the rising edge of the clock signal, ■ is a 1/2 period pulse that operates on the falling edge of the clock signal, and ■ is 1/2 period pulse that operates on the falling edge of the clock signal.
0, 5 extracted by Nando of /2 period pulse ■ and ■
Indicates a bit edge detection pulse. Edge detection pulse ■
is inserted into the 1024 frequency divider 3 as a load signal, initialized at the rising edge of the clock signal CK, counts the clock, and sends out the frame pulse FPI.

In the case of figure (a), the 1024 frequency divider cannot read the edge extraction pulse ■ at the rising edge of the clock, so
It is in a state of self-propulsion. Further, in the case of FIG. 13(b), the 1024 frequency divider periodically reads the edge extraction pulse (3) and is in a controlled state by the reference frame pulse FPO. Therefore, by comparing the case of FIG. 11A and the case of FIG.

On the contrary, in the case of Figure (c), the 1024 frequency divider is in a controlled state by the reference frame pulse FPO, and in the case of Figure (d), it is in a free running state. Comparing the cases in FIG. 3(C) and FIG. 3(d), it can be seen that the frame pulse FPI is stably output even when the reference frame pulse FPO includes jitter before and after the reference frame pulse FPO.

Through figures (a), (b), (c), and (d),
It was found that the frame pulse FPI is stably output with respect to jitter within 1.5 bit width of the reference frame pulse FPO between the rising edge of the clock signal *I and the falling edge of the clock signal *4. Pulse FPO
The phase difference between the output frame pulse and the output frame pulse FP1 is 0.5 to 1.0 bits in figure (a), and 1.0 to 1.5 bits in figure (b).
bits, 1.0 to 1.5 bits in figure (C), figure (d)
In this case, it is 1.5 to 2.0 bits, and the total is 0.5 to 2.
．． It can be within 0 bits.

〔Effect of the invention〕

According to the present invention, by matching the frame phases of each device, the phase difference in frame phases can be kept within 0.5 to 2.0 bits, and jitter within 1 to 5 bits can also be absorbed. , there is no signal delay in the multi-stage connection device, and an increase in memory capacity due to phase differences can also be avoided.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a timing chart of the present invention, Fig. 3 is a circuit block diagram of the embodiment, Fig. 4 is a timing chart of the embodiment, and Fig. 5 is a block diagram of the conventional example. The configuration diagram and FIG. 6 show a timing chart of a conventional example. In the figure, 1 and 11 are phase-locked oscillation circuits, 2 is an edge detection circuit, 3.13 is an n frequency divider, 12 is a memory, 21,
22.23.24 is a D-type flip-flop circuit, 25
is an inverter circuit, 26.27 is an AND circuit, and 28 is a NAND circuit.

Claims (1)

[Claims] A phase synchronized oscillation circuit (1) that inputs a reference frame pulse and generates a reference clock, and an edge detection circuit that detects the rising or falling edge of the reference frame pulse and generates a pulse 0.5 times the reference clock bit. Circuit (2)
and an n frequency divider (3) that loads an initial value using the output of the edge detection circuit and performs a counting operation using the reference clock.
outputs a synchronous frame pulse within a certain range width from the changing point of the input reference frame pulse, and eliminates jitter that occurs between the changing point of the reference frame pulse and the rising or falling point of the reference clock pulse. A frame phase synchronization circuit characterized by absorbing.