JP2969712B2 - Frame phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a frame phase synchronization circuit for synchronizing the phase of a signal frame between transmission apparatuses within a station and between transmission apparatuses at a distance from each other. A phase-locked oscillation circuit for generating a reference clock using a reference frame pulse for the purpose of adjusting the frame phase of the device, and detecting a rising or falling edge of the reference frame pulse, and 0.5 times the reference clock bit. A counting operation is performed using the edge detection circuit that generates a pulse and the reference clock, and a frame pulse is output, and counting is performed according to the high and low levels of the reference clock when the pulse generated by the edge detection circuit is present. It is configured to have a frequency divider that performs different processing whether to initialize the value.

[Industrial applications]

The present invention relates to a frame phase synchronization circuit for synchronizing the phase of a signal frame within a station and between transmission apparatuses at a distance between stations.

Data transmitted from the transmission device on the transmission side is multiplexed and transmitted by a signal frame synchronized with the clock signal on the transmission side, and the signal frame received by the transmission device on the reception side is frame-synchronized by the clock signal on the reception side. The data is sent to the receiving device. A frame phase synchronization circuit for synchronizing the reception frame with the transmission frame is provided in the transmission device on the reception side.

[Conventional technology]

The block diagram of the conventional frame phase synchronization circuit is shown in FIG.
Shown in the figure. In the figure, reference numeral 11 denotes a phase-locked oscillation circuit,
A reference frame pulse is input from the transmission device on the transmission side to generate a reference clock signal on the reception side. Reference numeral 12 denotes a memory which stores data synchronized with the reference clock signal from the transmission side transmission device and a reference frame pulse, and transmits data synchronized with the reference clock pulse and the reference frame pulse on the reception side to the reception side. Reference numeral 13 denotes an n-frequency divider that loads an initial value with a reference clock signal and a reference frame pulse generated by a phase locked oscillation circuit, counts the reference frame pulse on the receiving side, and inserts the reference frame pulse into a memory.

In the conventional frame phase locked loop, the phase locked oscillator
The reference clock signal on the receiving side generated from 11 is divided by n frequency divider 13
, The phase relationship between the reference frame pulse from the transmitting side and the output frame pulse from the receiving side is arbitrary, and the synchronization of the frame phase between the transmitting side apparatus and the receiving side apparatus is not performed. Absent.

FIG. 6 shows a timing chart of the phase relationship between the input side and the output side in the conventional receiving apparatus. In the figure, data on the input side is received at a fixed cycle by a reference frame pulse FP0, and data is sent to the output side at a fixed cycle by an output-side reference frame pulse FP1 sent from an n-frequency divider. Therefore, although the reference frame pulse FP0 on the input side and the reference frame pulse FP1 on the output side have the same period,
Since the phase relationship is arbitrary, the frame phase between the devices cannot be synchronized. For this reason, the received data is accumulated in the memory 12 until the initialization of the reference frame pulse on the output side, and the memory usage increases.

[Problems to be solved by the invention]

Therefore, in the conventional frame phase synchronization circuit, since a delay occurs due to phase synchronization, each apparatus in the station needs a delay for adjusting the input signal to the frame phase of the apparatus itself, and the transmission path in which the apparatuses are connected in multiple stages. However, there is a problem that the delay of the signal is increased in the communication using. In addition, there has been a problem that the capacity of the memory used in the apparatus is increased, and the mounting scale of the printed board is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a frame phase synchronization circuit having a small memory capacity capable of adjusting a frame phase of each device and reducing a delay for phase synchronization as much as possible.

[Means for solving the problem]

FIG. 1 shows a principle configuration diagram of the present invention. In the figure, 1
A phase-locked oscillation circuit that generates a reference clock using a reference frame pulse, an edge detection circuit that detects a rising or falling edge of the reference frame pulse and generates a pulse 0.5 times the reference clock bit, Performs a count operation using a reference clock, outputs a frame pulse, and initializes or does not initialize a count value according to the high and low levels of the reference clock when a pulse generated by the edge detection circuit exists. A frame phase synchronization circuit having a frequency divider having different processing is used.

[Action]

The phase-locked oscillation circuit generates a reference clock using the reference frame pulse. Further, the edge detection circuit detects a rising edge or a falling edge of the reference frame pulse, and generates a pulse 0.5 times the reference clock. The frequency divider performs a count operation using the reference clock, outputs a frame pulse, and initializes a count value according to the high and low levels of the reference clock when a pulse generated by the edge detection circuit exists. Do.

〔Example〕

FIG. 1 shows a principle configuration diagram of the present invention. In the figure, 1
Is a phase-locked oscillation circuit that receives a reference frame pulse and generates a reference clock, and 2 detects a rising or falling edge of the reference frame pulse and detects 0.5% of the reference clock.
An edge detector 3 for generating a doubled pulse is an n-divider that loads an initial value based on the output of the edge detector, performs a counting operation with a reference clock, and outputs a synchronous frame pulse.

FIG. 2 shows a timing chart of the present invention.

The figure shows a case where a frame pulse is detected based on the rising edge of a reference clock signal. FIG. 7A shows a case where control of the reference frame pulse is not performed, and FIG. 7B shows a case where control of the reference frame pulse is performed.

In the figure, FP0 is the reference frame pulse on the input side, CK
Is a clock signal generated from the phase-locked oscillation circuit 1, EG is a load pulse output from the edge detection circuit 2, COU is a count signal of the n frequency divider 3, and FP1 is a frame pulse output from the n frequency divider 3. Show.

If the reference frame pulse FP0 is inserted after the rising edge of the clock signal CK as shown in FIG. The pulse EG sends out a 0.5-bit sentence pulse at the next rising edge of the clock signal, but the count value COU starts counting from 0 without reading the load pulse EG. Therefore, the frame pulse FP1 is output without being controlled by the input frame pulse FP0.

Next, when the reference frame pulse FP0 is inserted before the rise of the clock signal CK as shown in FIG. 9B (when the reference point of the reference frame pulse changes at the phase when the clock is at the low level), The load pulse EG sends out a 0.5-bit sentence pulse in the clock signal.
The count value COU starts counting from 0 after being initialized by the load pulse EG. Accordingly, the frame pulse FP1 is output under the control of the input frame pulse FP0.

Therefore, regardless of whether the reference frame pulse FP0 is inserted after or before the rising edge of the clock signal CK, the load pulse EG transmits a 0.5-bit width pulse of the clock pulse CK, and the frame pulse FP1 is the reference frame pulse. F
It is sent within a certain range from the point of change of P0. Further, the reference frame pulse FP0 can transmit a stable frame pulse FP1 even if there is a jitter (deviation) with respect to the rise of the clock signal CK.

FIG. 3 shows a circuit diagram of an embodiment of the present invention. In the figure, 1 is a phase locked oscillation circuit, 2 is an edge detection circuit, 3
Indicates a 1024 divider.

The phase-locked oscillation circuit 1 is an oscillator that receives a reference frame pulse FP0 from the transmission side and generates a reference clock signal CK. Edge detection circuit 2 is a D-type flip-flop circuit
21, 22, 23, 24, an inverter circuit 25, AND circuits 26, 27, and a NAND circuit 28, and D-type flip-flop circuits 21, 2.
2 receives the reference frame pulse FP0 and operates in two stages in synchronization with the clock signal CK oscillated by the phase-locked oscillation circuit 1. D-type flip-flop circuits 23 and 24 receive the reference frame pulse FP0 and The clock signal CK oscillated by the synchronous oscillation circuit 1 operates in 23 stages in synchronization with an inverted signal of the inverter circuit 25. The AND circuit 26 sends out a 1/2 cycle pulse at the rise of the clock signal, and the AND circuit 2
7 sends out a 1/2 cycle pulse at the falling edge of the clock signal. The NAND circuit 28 receives the 1/2 cycle pulse and sends out a negative edge detection pulse. The 1024 frequency divider 3 is a counter for inputting the clock signal CK and transmitting a frame pulse of a period of 1/1024. The edge detection pulse from the edge detection circuit 2 is input as a load signal, and the counter value is initialized to 0. The frame pulse FP1 is output by 1024 count operations.

FIG. 4 shows a timing chart of the circuit operation of the embodiment. FIGS. 7A and 7B show the case where the reference frame pulse edge is detected at the rising edges * 1 and * 2 of the clock signal. FIGS. 7C and 7D show the case where the edge of the reference frame pulse is detected by the clock signal. In this case, the detection is performed at the falling edges * 3 and * 4. In each case, the reference frame signal is inserted with a delay with respect to the rising or falling edge of the clock signal and before the reference frame signal is inserted. Is shown.

In the timing chart, is a half-period pulse that operates at the rising edge of the clock signal, is a half-period pulse that operates at the falling edge of the clock signal, and is a 0.5-bit edge extracted by NAND with the half-period pulse 3 shows a detection pulse. The edge detection pulse is inserted into the 1024 frequency divider 3 as a load signal, is initialized at the rise of the clock signal CK, counts the clock, and transmits the frame pulse FP1.

In the case of FIG. 9A, the 1024 frequency divider cannot read the edge extraction pulse at the rising edge of the clock, and is in a self-running state. In the case of FIG. 7B, the 1024 frequency divider periodically reads the edge extraction pulse, and is in a control state by the reference frame pulse FP0. Therefore, a comparison between the case of FIG. 7A and the case of FIG. 7B shows that the frame pulse FP1 is stably output even when the reference frame pulse FP0 includes the preceding and following jitters.

Conversely, in the case of FIG. 9C, the 1024 frequency divider is in a control state by the reference frame pulse FP0, and in the case of FIG. Comparing the cases of FIGS. 9C and 9D, it can be seen that the frame pulse FP1 is stably output even when the reference frame pulse FP0 includes the preceding and following jitters.

(A), (b), (c) and (d), the jitter within the 1.5-bit width of the reference frame pulse FP0 between the rising edge of the clock signal * 1 and the falling edge * 4 of the clock signal. It can be seen that the frame pulse FP1 is output stably, and the phase difference between the reference frame pulse FP0 and the output frame pulse FP1 is 0.5 to 1.0 bits in FIG.
In FIG. (B), 1.0 to 1.5 bits, in FIG. (C), 1.0 to 1.5 bits, and in FIG. (D), 1.5 to 2.0 bits.
It can fit within 5 to 2.0 bits. Therefore, by adjusting the frame phase of each device, the phase difference between the frame phases can be within 0.5 to 2.0 bits, and the jitter within 1.5 bits can be absorbed, so that the increase in the memory capacity due to the phase difference is avoided. be able to.

〔The invention's effect〕

By using the frame synchronization circuit according to the present invention, the phase difference between the frame phases can be suppressed, the signal delay due to the multistage connection is eliminated, and the increase in the memory capacity due to the phase difference can be avoided.

[Brief description of the drawings]

1 is a block diagram of the principle of the present invention, FIG. 2 is a timing chart of the present invention, FIG. 3 is a circuit diagram of the embodiment, FIG. 4 is a timing chart of the embodiment, and FIG. FIG. 6 is a timing chart of a conventional example. In the figure, 1, 11 is a phase-locked oscillation circuit, 2 is an edge detection circuit, 3 and 13 are n frequency dividers, 12 is a memory, 21, 22, 23, and 24 are D
Type flip-flop circuit, 25 is an inverter circuit, 26, 27
Represents an AND circuit, and 28 represents a NAND circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 3/06 H04L 7/08

Claims (1)

(57) [Claims] 1. A phase-locked oscillation circuit for generating a reference clock using a reference frame pulse, and an edge detection for detecting a rising or falling edge of the reference frame pulse and generating a pulse 0.5 times the reference clock bit. A counter circuit performs a count operation using the reference clock, outputs a frame pulse, and initializes a count value according to a high or low level of the reference clock when a pulse generated by the edge detection circuit exists. A frequency divider which performs or does not perform processing differently.