JPH03196183A - Video processor - Google Patents

Abstract

PURPOSE:To insert a slave screen to a desired position and to always prevent deviation between a position to be found and an actual position occurring by supplying information with respect to the back porch period of a video signal on a master screen in advance, and hereinafter, supplying position information on the effective area of the master screen. CONSTITUTION:A control means 31 decides a timing to replace second video signals 8, 44 by R, G, and B luminance signals from a D/A conversion means setting a time when an internal back porch period in which the horizontal and vertical synchronizing signals HPSC, VPSC of the second video signals 8, 44 are set as an origin and set based on external information elapses as reference. Thereby, the internal back porch period can be conformed to the actual back porch period of the second video signals 8, 44 at that time even when the signal sources of the second video signals 8, 44 are different. Therefore, the slave screen 7 can be accurately inserted to the desired position by supplying the position information on the effective area of the master screen with respect to a position where the slave screen 7 is desired to insert. Thereby, the deviation between the position desired to find and the actual position can be eliminated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a video processing device that superimposes another video screen on a part of one video screen, and in particular, the present invention relates to a video processing device that superimposes another video screen on a part of one video screen. This invention relates to an image processing device that can be positioned at

[Conventional technology]

In the field of so-called personal computers (PCs), image processing called picture-in-picture, which displays television images superimposed on computer images, has become popular. In other words, by intervening between the computer and the computer monitor and taking in an external video signal (for example, an NTSC composite video signal) in addition to the computer video signal, the external video signal is displayed on a part of the computer video screen (main screen). Video processing devices that display screens (child screens) based on the above are being developed. In this case, the positioning of the child screen on the main screen is normally performed based on the timing of the horizontal and vertical synchronization signals of the main screen.

[Problem to be solved by the invention]

By the way, if the main screen is a computer video screen,
The back porch period differs somewhat depending on the model of the computer that is the video signal source. 9 and 10 both show personal computer video signals, with FIG. 9(a) showing a luminance signal and FIG. 9(b) showing a horizontal synchronizing signal. In the figure, a period T1 is a horizontal back porch period. In addition, Fig. 10(a) shows the horizontal synchronizing signal, and Fig. 10(b) shows the horizontal synchronizing signal.
denote horizontal synchronizing signals, and if period T3 is an effective scanning period of one field, period T2 is a vertical back porch period. The horizontal back porch period T1 and the vertical back porch period T2 differ depending on the model of the personal computer.

Therefore, in the conventional method in which the timing of inserting an external video signal to create a sub screen is determined simply based on the horizontal and vertical synchronization signals of the main screen, the timing of inserting an external video signal on the main screen depends on the model of the computer that is the signal source of the main screen. There are variations in the position of the child screen.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the video processing device of the present invention includes:
A/D conversion means for converting the RGB luminance signal of the first video signal into a digital RGB luminance signal; a video storage means for storing the digital RGB luminance signal from the A/D conversion means; and a video storage means for reading from the video storage means. a D/A converting means for converting the digital RGB luminance signal into analog; a mixing means for partially replacing the RGB luminance signal of the second video signal with the RGB luminance signal from the D/A converting means;
RG from the D/A conversion means during the screen of the video signal
and a control means for controlling each of the means based on a command indicating how to insert the screen based on the B brightness signal,
The control means controls the second video signal to D based on the point in time when an internal back porch period, which is set based on external information starting from the horizontal and vertical synchronization signals of the second video signal, has elapsed.
The timing for replacing the RGB luminance signal with the RGB luminance signal from the /A conversion means is determined.

[Effect]

Even if the signal source of the second video signal is different, the internal back porch period can be made to match the actual back porch period of the second video signal at that time.

Therefore, if positional information on the effective area of the parent screen is given regarding the position where the child screen is to be inserted, the child screen will be inserted exactly at the desired position, and there will be no deviation between the desired position and the actual position.

〔Example〕

FIG. 1 is a block diagram of a video processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the connection relationship between the video processing device, a personal computer, and a personal computer monitor.

The video processing device 1 receives a personal computer video signal 3 (RGB luminance signal and vertical/horizontal synchronization signal) coming from a personal computer 2 and an NT video signal coming from a video input terminal 4.
The SC composite video signal 5 is input. Then, the video processing device 1 synthesizes these two video signals and outputs a video signal 8, in which the screen 7 of the NTSC composite video signal 5 is inserted into the screen 6 of the PC video signal 3, to the computer monitor 9. How the screen 7 is inserted into the screen 6 is determined based on instructions 10 from the personal computer 2.

The NTSC composite video signal 5 is applied to the video input terminal 4 from a TV tuner, video deck, etc. (not shown).

Next, the internal configuration of the video processing device 1 will be explained.

The video signal decoder 21 is an NTS from the video input terminal 4.
A C composite video signal is input, and RGB luminance signals and horizontal and vertical synchronization signals are extracted from this video signal. The A/D converter (ADC) 22 converts the RGB luminance signal 23 coming from the video signal decoder 21 into a digital RGB luminance signal 25 at the timing of the clock signal CKAD from the digitizing control section 24 . Video memory 26 has 960 lines x 3
It has a configuration of 06 columns x 4 bits, and this is RlGSB.
are provided for each color.

The digitizing control section 24 sends a clock signal C to the ADC 22.
In addition to outputting KAD, a write control signal WETV is output to the video memory 26. The clock signal CKAD is a signal synchronized with the horizontal synchronization signal from the video signal decoder 21, and has a period of 1/1 of the period of the horizontal synchronization signal (for example, 63.5 μs).
It has a period of N (N is a positive integer). Write control signal WE
TV is a signal that allows writing of the digital RGB luminance signal 25 coming from the ADC 22. The specific form of the write control signal WETV varies depending on the specifications of the video memory 26, but for boat fishing, it is a set of a plurality of control signals. For example, a signal that specifies or advances a pixel address on the screen of the video memory 26, a control signal that allows writing in units of pixels on the screen of the video memory 26,
A control signal that permits writing only to a desired area on the screen of the video memory 26, a control signal that permits writing only to a desired area in the horizontal direction on the screen of the NTSC composite video signal 5, and a control signal that permits writing only to a desired area in the vertical direction on the screen of the NTSC composite video signal 5. It consists of control signals that permit writing. These control signals are all sent to the digitizing control section 24.
It is created by counting the write basic synchronization signals created inside the controller and changing the signal level when the count result reaches a set value. These set values can be adjusted based on instructions from the personal computer 2. By appropriately selecting these setting values, it becomes possible to arbitrarily specify resolution, aspect ratio, etc. In addition, the counting for creating each control signal is
It is reset every vertical synchronization signal of the NTSC composite video signal 5. Therefore, writing of a 2:1 interlaced video signal such as the NTSC composite video signal 5 in which a vertical synchronization signal is inserted for each field is performed in units of fields.

The superimpose control unit 31 controls reading of video data stored in the video memory 26.

This superimpose control unit 31 sends a read control signal to the video memory 26 based on the conditions commanded from the personal computer 2, and outputs a read control signal to the D/A converter (DAC).
A clock signal CKDA is sent to the video switch 31, and an enable signal 42 is sent to the video switch 34. The reading of video data by the superimpose control section 31 is performed completely independently of the writing by the digitization control section 24. The internal structure of the superimpose control section 31 will be described later in conjunction with FIG.

The DAC 32 samples the digital RGB luminance signal 40 read from the video memory 26 at the timing of the clock signal CADA and converts it into an analog RGB luminance signal 41.

The video switch 34 has a superimpose permission signal 4.
2, the analog RGB luminance signal output from the DAC 32 is superimposed on the RGB luminance signal of the PC video signal 3 arriving from the input terminal 35, and output as a new RGB luminance signal 44.

The video signal output terminal 38 is connected to the R from the video switch 34.
This terminal outputs the GB luminance signal 44 and the horizontal and vertical synchronization signals from the video signal hexagonal terminal 35, and the video signal 8 (RGB luminance signal and synchronization signal) from this output terminal 38 is given to the computer monitor 9. .

Here, the superimpose control section 31 will be explained in detail. FIG. 3 is a block circuit diagram of the superimpose control section 31 and its peripheral circuits shown in FIG. 1. The video memory 26 shown in Figure 4 is Sony CXK1206.
and the second part of its data sheet number 71215-ST
Timing charts related to read ports are described on pages 7 to 31. The boat used is read boat 1 on page 2 of the above data sheet.

In the video memory 26, the memory drive clock signal HDCK
is the port 1 shift signal terminal CKR1, and the memory vertical/horizontal reset signal MR8T is the port 1 vertical clear terminal VC.
The horizontal direction reset signal HRST is applied to LRI, and the vertical offset signal VOF is applied to the boat 1 horizontal clear terminal HCLR1.
T or vertical line clock signal VLCK is connected to the boat 1 line increment terminal lNCl, and the boat 1 output signal enable REI (negative logic) is connected to the boat 1 output signal enable terminal R.
Each is given to EI (negative logic). Also, analog R
The GB signal LSMEM (one data in each of R, G, and B) is read from the boat 1 data output DO-DO13.

0 Port 1 shift signal CKR1, port 1 vertical clear VCLRI, port 1 horizontal clear signal HCLRI, port 1 line increment signal INC corresponding to each of the above terminals
l. Due to boat 1 output enable REI (negative logic),
The analog RGB signal LSMEM to be read is controlled by R,
For example, 4 bits are output for each of G and B from the port 1 data output DO and o-Do13, respectively.

The video switch 34 has a switching signal CNT (-superimpose permission signal 42) inputted to a switching signal input terminal.
As a result, the input from the A terminal or the B terminal is output from the common terminal C. Specifically, the switching signal CNT is at high level rH.
When the level is J, the input from the B terminal is output from the C terminal, and when the low level is rLJ, the input from the A terminal is output from the C terminal.

CPU bus 610 is connected to personal computer 2 . Reference numeral 420 is a horizontal back porch end signal H
421 shows a horizontal internal back porch setting counter that outputs BE, and 421 is a horizontal reference read dot clock signal HBDC.
422 represents a horizontal read start counter that outputs a horizontal read start A signal HRSA and a horizontal read direction reset signal HRST, and 423 outputs a horizontal reference start B signal HR5B. A horizontal 64 clock counter is shown, 424 is a horizontal read number counter that outputs a horizontal read number signal HRT, and 425 is a horizontal read dot clock generator that outputs a horizontal successive dot clock signal HDDA.

Further, the memory vertical read offset counter 426 has a function of arbitrarily setting the count number of the horizontal reference read dot clock generator 421 from the personal computer 2, and outputs a vertical read offset signal VROFT. The vertical internal back porch setting counter 427 outputs the vertical back porch end signal VBE, the vertical read start counter 428 outputs the vertical read start signal VR6, and the vertical read count counter 429 outputs the vertical read count signal VRT, and the vertical read start counter 428 outputs the vertical read count signal VRT. Line clock generator 430 outputs a vertical read line clock signal VRLCK. AND circuit 4
31 outputs a superimpose enable signal 5ENBL, and an OR circuit 432 outputs a vertical read offset signal VTOFT.
or the vertical read line increment signal VRLCK as the vertical read clear signal VCLRI, and the NOR circuit 433 outputs the read enable REI signal. Further, reference numerals 434 and 435 indicate tri-state circuits, and 436 indicates an inverter circuit.

Analog RGB luminance signals coming from a color input terminal 506 forming part of the video input terminal 35 are applied to the A terminal of the video switch 34. The horizontal synchronization signal H8PC arriving from the synchronization terminal 507 forming a part of the input terminal 35 is applied to the horizontal internal back porch setting counter 420, the horizontal reference successive dot clock generator 421, and the horizontal read start counter 422.
, horizontal 64 clock counter 423, horizontal read count counter 424, horizontal read dot clock 425, vertical internal back porch setting counter 427, vertical read start counter 428, vertical read count counter 429, and vertical read line clock generator 430. , is sent to a synchronization signal terminal 490 forming part of the output terminal 38. Further, the vertical synchronization signal vspc arriving from the synchronization terminal 508 forming a part of the input terminal 35 is transmitted to the video memory 26, the vertical offset counter 426, the vertical internal back porch setting counter 427, the vertical read start counter 428, and the vertical read number counter 429. , vertical read line clock generator 4
30 and sent to a synchronization signal terminal 491 forming a part of the output terminal 38.

The horizontal internal back porch setting counter 420, the horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read circuit counter 424 are controlled by the horizontal synchronization signal H3P.
The count value is reset by C. A vertical read offset counter 426, a vertical internal back porch setting counter 427, a vertical read start counter 428, and a vertical read count counter 429 are connected to a vertical synchronization signal VS.
The count values are each reset by the PC.

The signal HBDCK generated by the horizontal reference read dot clock generator 421 is applied to a horizontal internal back porch setting counter 420, a horizontal read start counter 422, a horizontal 64 clock counter 423, a horizontal read count counter 424, and a vertical read offset counter 426. At the same time,
The port 1 of the video memory 26 is output as the clock signal HDCK of the video memory 26 via the tri-state circuit 435.
The signal is sent to the shift signal terminal CKRI.

Further, the horizontal read dot clock generator 425 is composed of a PLL circuit that synchronizes with the horizontal synchronizing signal HSPC and outputs a signal with a frequency N1 times the frequency of the horizontal synchronizing signal H8PC, and outputs the horizontal read dot clock signal HDDA. do. The horizontal read dot clock signal HDDA generated by the horizontal read dot clock generator 425 is applied to the port 1 shift signal terminal CKRI of the video memory 26 and the DAC 410 as the clock signal HDCK of the video memory 26 via the tri-state circuit 434. It is used as a read clock signal for the digital RGB luminance signal LSMEM and a conversion clock signal for the DAC 410.

Furthermore, the vertical read line clock generator 430 is configured with a PLL circuit that is synchronized with the vertical synchronizing signal vspc and outputs a signal with a frequency N2 times the frequency of the vertical synchronizing signal VSPC, and is synchronized with the vertical read line clock signal VRLCK.
Output. This vertical read line clock generator 430
The vertical read line clock signal VRLCK generated from the port 1 is synchronized with the clock signal HDCK of the video memory 26, and advances the line address, which is the vertical address of the video memory 26, via the OR circuit 432 to the boat 1 line increment terminal lNCl. is given to O
It is applied to the port 1 output enable REI terminal (negative logic) via the R circuit 432 and the NOR circuit 433.

The superimpose control unit 31 controls the horizontal reference read dot clock signal HBDCK, the horizontal read dot clock signal HDDA, and the vertical read line clock signal VRL.
CK provides basic timing.

Further, in order to determine the read start offset point of the video memory 26, the vertical read offset counter 426 resets the count value by the vertical synchronization signal vspc, and then uses the horizontal reference read dot clock output from the horizontal reference read dot clock generator 421. A vertical offset signal VOFT that increments the vertical line address of the video memory 26 is sent to the OR circuit 432 in synchronization with the signal HBDCK.

Further, the vertical internal back porch setting counter 427 includes a counter for deleting the vertical back porch area of the analog RGB luminance signal LSPC. FIG. 4 is a block diagram showing the internal configuration of the vertical internal back porch setting counter 427, in which a counter circuit 601, a comparison circuit 602
and a set value storage circuit 603. The counter 601 receives a horizontal synchronizing signal H applied to an input terminal 605.
Count the number of clocks on 3PC. On the other hand, the setting value storage unit 603 stores numerical values given from the personal computer 2. This value is the horizontal synchronization signal H
It is given from the personal computer 2 so that the value multiplied by the period of 8PC becomes the vertical back porch of the personal computer video signal output from the personal computer 2. Comparison circuit 602 compares the value from set value storage section 603 and the value from counter 601, and outputs a match signal 608 when the value from counter 601 matches the value from set value storage section 603. This match signal 608 is output from the output terminal 607 as the vertical back porch end signal VBE. Note that the counter 601 is reset by the vertical synchronization signal VSPC from the input terminal 606.

Since the vertical internal back porch setting counter 427 is configured in this way, the time point when the vertical back porch period of the PC video signal has passed and the vertical back porch end signal V
The time point when BE is output to the vertical read start counter 428 (
Vertical internal back porch ends). Vertical read start counter 428 receives this permission signal (vertical back porch end signal VBE) and outputs horizontal synchronizing signal H5.
It counts the number of clocks of the PC and outputs a vertical read start permission signal (vertical read start signal) from the video memory 26 to the VH5 vertical read count counter 429. The vertical reading number counter 429 is the vertical reading start counter 42
8 receives the permission signal (control signal VRS) sent from the video memory 26, counts the number of clocks of the horizontal synchronizing signal HSPC, and outputs a signal indicating the read period in the vertical direction from the video memory 26, that is, a vertical read count signal VRT, to an AND circuit. 43
Output to 1.

Then, the vertical read offset counter 4 described above
26, vertical internal back porch setting counter 427, vertical reading start counter 428, vertical reading number counter 429
A vertical read line clock generator 430 controls reading of the video memory 26 in the vertical direction.

Note that the number of clocks of the horizontal reference read dot clock signal HBDCK counted by the vertical read offset counter 426, the number of clocks of the horizontal synchronization signal HSPC counted by the vertical read start counter 428, and the number of clocks of the horizontal synchronization signal H3PC counted by the vertical read number counter 429. As with the vertical internal back porch setting counter 427, each clock number is set to a required value by an instruction from the personal computer 2.

On the other hand, horizontal internal back porch setting counter 420 counts the number of clocks of horizontal reference read dot clock signal HBDCK sent from horizontal reference read dot clock generator 421, and outputs horizontal back porch end signal HBE. This horizontal internal back porch setting counter 420
is the vertical internal back porch setting counter 4 shown in FIG.
Since it has the same internal configuration as 27, its illustration is intentionally omitted and the explanation will be made using FIG. 4 instead.

Horizontal reference read dot clock signal HBDCK is applied to input terminal 605, and when the count number of counter 601 matches the value stored in set value storage section 603, comparison circuit 602 outputs a match signal 608. Match signal 6
08 is output from the output terminal 607 as the horizontal back porch end signal HBE. The output terminal 607 is connected to the input terminal of the horizontal read start counter 422 . The values stored in the setting value storage section 603 are given from the personal computer 2. This value is given by the personal combinator 2 so that the value multiplied by the period of the horizontal reference read dot clock signal HBDCK matches the horizontal back porch of the PC video signal. Note that the counter 601
is the horizontal synchronizing signal HSPC applied to the input terminal 606
It is reset by .

The horizontal read start counter 422 starts counting the number of clocks of the horizontal reference read dot clock signal HBDCK sent from the horizontal reference read dot clock generator 421 after inputting the horizontal back porch end signal HBE, and the count number reaches the set value. When the readout start permission signal (horizontal readout start A signal HRSA) for the horizontal direction of the video memory 26 is reached,
) is sent to the horizontal 64 clock counter 423. Horizontal 64 clock counter 423 is horizontal read start counter 4
22 (horizontal read start A signal HR
SA), the horizontal reference readout dot clock generator 4
Horizontal reference read dot clock signal H output from 21
Count the number of BDCK clocks. When the count value reaches 64 clocks, which is the characteristic when reading from the video memory 26, a horizontal read start B signal HRSB is output to the horizontal read number counter 424 and the AND circuit 431. The horizontal readout number counter 424 counts the number of clocks of the horizontal reference readout dot clock signal HBDCK sent from the horizontal reference readout dot clock generator 421, and calculates the readout period permission signal (for the horizontal direction of the video memory 26).
The horizontal read count signal HRT) is sent to the AND circuit 431.

Thus, the horizontal internal back porch setting counter 420,
A horizontal reading start counter 422, a horizontal 64 clock counter 192, and a horizontal reading port number counter 424 perform horizontal reading control for the video memory 26. Note that the number of clocks of the horizontal reference read dot clock signal HBDCK counted by the horizontal read start counter 422 and the number of clocks of the reference dot clock signal HBDCK counted by the horizontal read number counter 424 are the same as the number of clocks of the horizontal internal back porch setting counter 420. Similarly, the personal computer 2 sets the respective required values.

Next, regarding the operation of the superimpose control unit 31,
This will be explained with reference to FIGS. 5, 6, 7, and 8. 5 is a timing chart for vertical reading permission of the video memory 26, and FIG. 6 is a timing chart for vertical reading permission of the video memory 26.
FIG. 7 is a timing chart of horizontal reading permission of the video memory 26, and FIG. 8 is a timing chart of horizontal reading of the video memory 26.

First, regarding permission to read the video memory 26 in the vertical direction,
This will be explained with reference to FIG.

When the vertical synchronization signal vspc reaches the high level rHJ (see FIG. 5(a)), the vertical internal back porch setting counter 427, the vertical read start counter 428, and the vertical read number counter 429 are reset, and the vertical back porch end signal VBE, The vertical read start signal VRS and the vertical read count signal VRT each become low level "L" (see FIGS. 5(d), (e), and (f)), and the vertical internal back porch setting counter 427 outputs the horizontal synchronizing signal H8PC. counts the number of clocks, and when it reaches a predetermined value, sets the vertical back porch end signal VBE to high level rHJ (Fig. 5(d)
)reference). When the vertical back porch end signal VBE reaches the high level rHJ, the vertical read start counter 428 starts counting the number of clocks of the horizontal synchronizing signal HSPC.

When the vertical read start counter 428 counts the value set by the personal computer 2, the vertical read start signal VR8 is set to high level rHJ (FIG. 5(e)).
reference). When the vertical read start signal VR8 becomes high level rHJ, it is permitted to start reading the digital RGB signal LSMEM in the vertical direction of the video memory 26, so the vertical read number counter 429 changes to the horizontal synchronizing signal H8PC. Start counting the number of clocks.

When the vertical read count counter 429 counts the value set by the personal computer 2, the vertical read count signal VRT is set to high level rHJ (see FIG. 5(f)).

During the period when the vertical read start signal VR3 is at high level rHJ and the vertical read count signal VRT is at low level rLJ, the horizontal read start B signal HRSB is at high level "H" and the horizontal read count signal HRT is at low level rLJ. If so, the AND circuit 431 outputs a superimpose enable signal 5ENBL of high level rHJ. Therefore, in the video memory 26, the digital RGB signal LSMEM is read out based on permission for continuous output in the vertical direction during this period.

Next, regarding the vertical offset of the video memory 26, the sixth
This will be explained with reference to the figures.

When the vertical synchronization signal vspc becomes high level rHJ (see FIG. 6(a)), the vertical read offset counter 426
After being reset, it starts counting the number of clocks of the horizontal reference read dot clock signal HBDCK. While counting the value set by the personal computer 2, the vertical read offset counter 426 applies the vertical read offset signal VROFT to the boat line increment lNCl of the video memory 26 via the OR circuit 432 (see FIG. 6(c)). , offset the vertical read address value of the video memory 26.

At this time, since the vertical synchronization signal VSPC and the vertical read offset signal VROFT are applied to the NOR circuit 433, the read enable signal RE1 (negative logic) is applied to the read enable terminal REI (negative logic) of the video memory 26, and the read It is allowed. Then, since a vertical offset is performed when the value set by the personal computer 2 is counted, the vertical read offset counter 4
26 stops outputting the vertical read offset signal VROFT until the arrival of the next vertical synchronization signal vspc.

Next, permission to read the video memory 26 in the horizontal direction will be explained with reference to FIG.

When the horizontal synchronization signal H3PC is output, the horizontal internal back porch setting counter 420 and the horizontal read start counter 42
2. The horizontal 64 clock counter 423 and horizontal read count counter 424 are reset, and the horizontal back porch end signal HRB, horizontal read start A signal HRSA, horizontal read start B signal HR5B, and horizontal read count signal HRT become low level rLJ. (Fig. 7(d), (e), (f).

(See g>). Therefore, the horizontal internal back porch setting counter 420 is connected to the horizontal reference readout dot clock generator 42.
1 outputs the horizontal reference read dot clock signal HBDC.
K clocks are counted, and when the count value reaches the value set by the personal computer 2, the horizontal back porch end signal HRB is set to high level rHJ (see FIG. 7(d)). This point coincides with the end point of the horizontal back porch of the PC video signal input from the input terminal 35. Horizontal back porch end signal HRB
When becomes high level rHJ, horizontal read start counter 4
22 counts the number of clocks of the horizontal reference read dot clock signal HBDCK, and when the count value reaches a preset value, sets the horizontal read start A signal HRSA to high level rHJ (see FIG. 7(e)). When the horizontal read start A signal HR8A becomes high level rHJ, the horizontal 64 clock counter 423 outputs the reference read dot clock signal HB.
Counting of the number of DCK clocks is started, and when the count value reaches 64, the horizontal read start B signal HRSB is set to high level rHJ (see FIG. 7(f)). Note that, due to the characteristics of the video memory 26, the horizontal 64 clock counter 423 receives the horizontal read start B signal HRSB at a count value of "64".
, and is not limited to 64.

When the horizontal read start B signal HRSB reaches the high level rHJ, it means that reading of the video memory 26 in the horizontal direction is permitted, and the horizontal read count counter 424 starts counting the number of clocks of the horizontal reference read dot clock signal HBDCK. When the count value reaches a preset value, the horizontal successive number signal HRT is set to high level rHJ (
(See Figure 7(g)).

When the vertical read start signal VRS is at high level rHJ and the vertical read count signal VRT is at low level rLJ, the period during which the horizontal read start B signal HR8B is at high level rHJ and the horizontal read count signal HRT is at low level rLJ AND circuit 4 receiving the horizontal read count signal HRT
31 outputs a superimposition enable signal 5ENBL of high level rHJ.

Next, regarding horizontal reading of the video memory 26,
This will be explained with reference to FIG.

Superimpose enable signal 5ENBL is at high level r
HJ (see FIG. 8(c)), based on the clock of the horizontal read dot clock signal HDDA outputted by the horizontal read dot clock generator 425 (see FIG. 8(b)).
, reading of the digital signal LSMEM from the video memory 26 and analog conversion by the DAC 32 are performed. The read enable signal REI at this time is also shown (see FIG. 8(d)).

On the other hand, as described above, the analog RGB signal LSPC arriving from the color input terminal 506 is input to the point A of the video switch 34. Also, it is read out from the video memory 26 and the DA
Analog RGB signal L converted to analog by C32
SDA is input to point B of the video switch 34.

Therefore, by switching the video switch 34 by the superimpose enable signal 5ENBL, the analog RGB signal LSMON, which is the output of the video switch 34, becomes the analog RGB signal LSP arriving from the color input terminal 506.
The signal LSMON is outputted from the output terminal 505 as a signal LSMON corresponding to an image obtained by superimposing an image corresponding to the analog-converted RGB signal LSDA into the image corresponding to C.

In addition, along with the output of the analog RGB signal LSMON,
The horizontal synchronization signal and vertical synchronization signal vspc are also output terminal 38
(including output terminal 505).

Note that the above-mentioned timing chart is an example, and the above-mentioned operation can be performed even if each signal is positive logic or negative logic.

Furthermore, as can be seen from the configuration in FIG.
36, the tristate circuit 434 operates and the horizontal read dot clock signal HDDA is output to the drive clock signal H.
Sent as DCK. Conversely, when superimposition enable signal 5ENBL is at low level rLJ, tristate circuit 435 operates and horizontal reference read dot clock signal HBDCK is applied to video memory 26 as drive clock signal HDCK.

That is, when superimposition is performed when the superimposition enable signal SENBL is at high level rHJ, the video memory 26 is accessed by the horizontal readout dot clock HDDA output from the horizontal readout dot clock generator 425, and the superimposition is performed. The digital RGB signal LSMEM is read out at a sufficient speed. On the other hand, when the superimpose enable signal 5ENBL is at a low level rLJ and superimposition is not performed, a horizontal reference read dot clock whose frequency is 100 times higher than the horizontal read dot clock HDDA output from the horizontal reference read dot clock generator 421 is generated. The video memory 26 is accessed by HBDCK, the address is incremented to the vertical readout offset point, and the digital RGB signals in the horizontal/vertical area where superimposition is not performed are simply skipped, and the next superimposition is performed. This prepares for the timing when the enable signal 5ENBL becomes high level rHJ.

Through this operation, it is possible to obtain a composite screen in which a sub-screen 7 based on an external video signal is inserted into a main screen 6 based on a personal computer video signal, as shown in the personal computer monitor 9 in FIG.

〔Effect of the invention〕

As explained above, according to the image processing device of the present invention, information regarding the back porch period of the video signal of the main screen is provided in advance, and after that, information regarding the position where the child screen is to be inserted is determined on the effective area of the main screen. If position information is provided, the sub-screen will be inserted exactly at the desired position each time, and there will always be no discrepancy between the desired position and the actual position.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an application example of this embodiment, FIG. 3 is a block diagram showing the internal configuration of a superimpose control section, and FIG.
The figure is a block diagram showing the internal configuration of the vertical and horizontal internal back porch setting counters, Figures 5 to 8 are waveform diagrams showing the operation of the superimpose control section, and Figure 9 is a waveform showing the horizontal PC video signal. 10 are waveform diagrams showing vertical PC video signals. DESCRIPTION OF SYMBOLS 1...Video processing device, 2...Personal computer, 3...PC video signal, 5...NTSC composite video signal, 6...Main screen, 7...Subscreen, 9...
PC monitor, 21... video signal decoder, 22...
...ADC. 24... Digitization control unit, 26... Video memory,
31...Superimpose control unit, 32...DA
C. 34...Video switch, 35...Video input terminal,
38... Video output terminal, 420... Horizontal internal back porch setting counter, 427... Vertical internal back porch setting counter, 601... Counter, 602...
Comparison circuit, 603... set value storage section.

Claims (1)

[Scope of Claims] A/D conversion means for converting the RGB luminance signal of the first video signal into a digital RGB luminance signal; video storage means for storing the digital RGB luminance signal from the A/D conversion means; D/A converting means for analogizing the digital RGB luminance signal read from the video storage means; and mixing means for partially replacing the RGB luminance signal of the second video signal with the RGB luminance signal from the D/A converting means. and a control means for controlling each of the means based on a command indicating how to insert a screen according to the RGB luminance signal from the D/A converting means into the screen according to the second video signal. In the processing device, the control means adjusts the second video signal to the D based on a point in time when an internal back porch period, which is set based on external information starting from horizontal and vertical synchronization signals of the second video signal, has elapsed. A video processing device that determines the timing of replacing with the RGB luminance signal from the /A conversion means.