JPS61255386A - Display unit - Google Patents

Display unit

Info

Publication number
JPS61255386A
JPS61255386A JP60098690A JP9869085A JPS61255386A JP S61255386 A JPS61255386 A JP S61255386A JP 60098690 A JP60098690 A JP 60098690A JP 9869085 A JP9869085 A JP 9869085A JP S61255386 A JPS61255386 A JP S61255386A
Authority
JP
Japan
Prior art keywords
vsc
back porch
video signal
hbp
appears
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60098690A
Other languages
Japanese (ja)
Other versions
JPH0833723B2 (en
Inventor
孝博 大出
豊 赤堀
佳司 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60098690A priority Critical patent/JPH0833723B2/en
Publication of JPS61255386A publication Critical patent/JPS61255386A/en
Publication of JPH0833723B2 publication Critical patent/JPH0833723B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔技術分野〕 (11本発明はORT (0athods Ray T
ube )セパレート信号とドツトクロックを基にVB
P。
[Detailed Description of the Invention] [Technical Field] (11 The present invention relates to ORT (0 methods Ray T
ube) VB based on separate signal and dot clock
P.

HBPを検出するu路を肩する表示装置に関するもので
ある。
The present invention relates to a display device that detects HBP.

〔従来技術〕[Prior art]

(2)一般にVBP、HBPはパソコン、その他の機器
によって異なるのはもちろんであるが、同じパソコンや
機器においてもソフトウェアによって変わってしまう場
合がある。VBP、HBPが変われば画面の位置がずれ
るのだがCRTを使用する場合においてはそれほど気に
ならないものである。しかしながらフレームメモリ等を
VSa。
(2) In general, VBP and HBP naturally differ depending on the personal computer or other equipment, but they may also change depending on the software even in the same personal computer or equipment. If the VBP and HBP change, the screen position will shift, but this is not a big concern when using a CRT. However, frame memory etc. are VSa.

HBC,ドツトクロックを基準に駆動する場合にnVB
P、HBPの変化は深刻である。
When driving based on HBC, dot clock, nVB
The changes in P and HBP are profound.

〔目 的〕〔the purpose〕

(8)本発明は上記のような機器、ソフトウェア等によ
って変化するVBP、HBPの変化に対応する念めのも
のであシ、自動的[VBP、HBPを検出して、フレー
ムメモリ等を常に正常に動作させることを目的とする。
(8) The present invention is a precautionary measure to deal with changes in VBP and HBP caused by equipment, software, etc. as described above, and automatically detects VBP and HBP to ensure that frame memory etc. are always in normal condition. The purpose is to make it work.

〔概 要〕〔overview〕

(4)本発明のVBPの検出は、パーンナルコンピュー
タかその他の機器から出力されるVSC。
(4) VBP detection according to the present invention is performed by VSC output from a personal computer or other equipment.

1180、映像信号のみを必要とすることを特徴とし、
VSC後最初に出現する映像信号を基に行なわれる。H
BPの検出は、VSO,H2C,ドツトクロック、映像
信号のみを必要とすることを特徴とし、HSC後最初に
出現する映像信号を基VC行なわれる。
1180, is characterized by requiring only a video signal,
This is performed based on the video signal that appears first after VSC. H
BP detection is characterized in that only VSO, H2C, dot clock, and video signals are required, and VC is performed based on the video signal that appears first after HSC.

〔実施例〕〔Example〕

(5)以下、本発明について一実施例を示す図面に従い
詳細に説明する。
(5) Hereinafter, the present invention will be described in detail with reference to the drawings showing one embodiment.

本発明を適用して構成したVBP検出回路の一実施例の
(ロ)略図を第1図に示す。またそのタイミングチャー
トを第2図に示す。
FIG. 1 shows a (b) schematic diagram of an embodiment of a VBP detection circuit configured according to the present invention. Moreover, the timing chart is shown in FIG.

第1図において1段目のFlip−Flop (以下F
、Fと略す)はVSCの立ち上りでセットされ、映像信
号が出現するとともにリセットされる。2段目のカウン
ターは1段目のF、11’がセットされた時からH2O
のカウント全開始し、リセットになった時点でカウント
を停止する。この時のカウンタの値はVSC刀)ら最初
の映像信号が出現する間のラスタ数である。この値をV
SCを適当に遅らせたVSCDELAY信号でラッチし
てやることでV B P 栄傅ることができる。VSC
D]T!LAY信号で同時にカウンタもリセットしてお
き、次のVSCがくると再び同じ動作をくり返す。続い
て、不考案を適用して構成したHBP検出回路の一実施
例の回路図を第5図に示す。またそのタイミングチャー
トを第4図に示す。第5図において1段目のF、FはH
2Cの立ち上りでセットされ映像信号の出現とともにリ
セットされる。カウンタはこの間のドツトクロック数を
カウントして停止する。
In Figure 1, the first stage Flip-Flop (hereinafter F
, F) are set at the rising edge of VSC and reset when the video signal appears. The second stage counter is H2O from the time F, 11' of the first stage is set.
The count starts completely and stops when it is reset. The value of the counter at this time is the number of rasters during which the first video signal appears from VSC. This value is V
By latching SC with an appropriately delayed VSCDELAY signal, VBP can be controlled. VSC
D] T! The counter is also reset at the same time by the LAY signal, and the same operation is repeated again when the next VSC comes. Next, FIG. 5 shows a circuit diagram of an embodiment of an HBP detection circuit constructed using an unconventional method. Further, the timing chart is shown in FIG. In Figure 5, F and F in the first row are H
It is set at the rising edge of 2C and reset when the video signal appears. The counter counts the number of dot clocks during this period and stops.

その値をH2Cを適当に遅らせたH80  DELAY
1信号でラッチしてやることでそのラスク内で最初に出
現する映像信号筒でのドツトクロック数を得ることが出
来る。この動作を1フレーム〈υ返し、その中の値で最
小のもの’1HBPとして採用する。
H80 DELAY which delayed H2C appropriately
By latching with one signal, it is possible to obtain the number of dot clocks in the video signal cylinder that appears first in the rask. This operation is returned for one frame 〈υ, and the smallest value among them is adopted as '1HBP.

〔効 果〕〔effect〕

L6)  以上の実施例から明らかなように、本考案に
よれば、VBP、HBPの検出を自動的に行なうことが
できる。そのため、テレビジョンセパレート信号のVB
P、HBPが変化するような場合でもフレームメモリの
駆動基準の設定を自動化することができる。
L6) As is clear from the above embodiments, according to the present invention, VBP and HBP can be automatically detected. Therefore, the VB of the television separate signal
Even when P and HBP change, the setting of the frame memory drive standard can be automated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を適用したVBPの検出回路の一実施例
で、第2図はそのタイミングチャートである。 第3図は本発明を適用したHBP検出回路の一実施例で
、第4図はそのタイミングチャートである。 以   上
FIG. 1 shows an embodiment of a VBP detection circuit to which the present invention is applied, and FIG. 2 is a timing chart thereof. FIG. 3 shows an embodiment of the HBP detection circuit to which the present invention is applied, and FIG. 4 is its timing chart. that's all

Claims (1)

【特許請求の範囲】[Claims] パーソナルコンピュータかその他の機器から出される垂
直同期信号(以下VSCと略す)、水平同期信号(以下
HSCと略す)、映像信号のみを用いて、VSC後最初
に出現する映像信号を基に垂直バックポーチ(以下VB
Pと略す)を検出する垂直バックポーチ自動検出回路と
、VSC、HSC、映像信号とドットクロックのみを用
いてHSC後最初に出現する映像信号を基に水平バック
ポーチ(以下HBPと略す)を検出する水平バックポー
チ検出自動検出回路とを備えることを特徴とする表示装
置。
Using only the vertical synchronization signal (hereinafter referred to as VSC), horizontal synchronization signal (hereinafter referred to as HSC), and video signals output from a personal computer or other equipment, the vertical back porch is created based on the first video signal that appears after VSC. (Hereafter VB
Using only the vertical back porch automatic detection circuit that detects the vertical back porch (abbreviated as P), VSC, HSC, video signal, and dot clock, detects the horizontal back porch (hereinafter abbreviated as HBP) based on the video signal that appears first after HSC. A display device comprising: a horizontal back porch detection automatic detection circuit.
JP60098690A 1985-05-09 1985-05-09 Display device Expired - Lifetime JPH0833723B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60098690A JPH0833723B2 (en) 1985-05-09 1985-05-09 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60098690A JPH0833723B2 (en) 1985-05-09 1985-05-09 Display device

Publications (2)

Publication Number Publication Date
JPS61255386A true JPS61255386A (en) 1986-11-13
JPH0833723B2 JPH0833723B2 (en) 1996-03-29

Family

ID=14226504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60098690A Expired - Lifetime JPH0833723B2 (en) 1985-05-09 1985-05-09 Display device

Country Status (1)

Country Link
JP (1) JPH0833723B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03196183A (en) * 1989-12-26 1991-08-27 Seiko Epson Corp Video processor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5463626A (en) * 1978-09-27 1979-05-22 Hitachi Ltd Crt display device
JPS55153275A (en) * 1979-05-16 1980-11-29 Toshiba Corp Power converter
JPS58221890A (en) * 1983-04-06 1983-12-23 株式会社日立製作所 Display unit
JPS60128393U (en) * 1984-02-06 1985-08-28 日本ボードコンピュータ株式会社 Video memory control device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5463626A (en) * 1978-09-27 1979-05-22 Hitachi Ltd Crt display device
JPS55153275A (en) * 1979-05-16 1980-11-29 Toshiba Corp Power converter
JPS58221890A (en) * 1983-04-06 1983-12-23 株式会社日立製作所 Display unit
JPS60128393U (en) * 1984-02-06 1985-08-28 日本ボードコンピュータ株式会社 Video memory control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03196183A (en) * 1989-12-26 1991-08-27 Seiko Epson Corp Video processor

Also Published As

Publication number Publication date
JPH0833723B2 (en) 1996-03-29

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