JPS59154886A - Access method of display memory in character broadcast receiver - Google Patents

Abstract

PURPOSE:To attain efficient processing operation by utilizing time gap unnecessary for the hardware even during the hardware read cycle period and accessing the software to a display memory. CONSTITUTION:A television signal superimposed with a character signal is applied to a character extracting circuit 4 and a synchronous separating circuit 5 via an antenna 1, a tuner 2 and a video detecting circuit 3. Only a character signal is extracted from the character extracting circuit 4, converted into a 8-bit parallel data through a serial/parallel shift register 6 and written in a buffer memory in a display memory 7. After the character signal stored in the buffer memory is processed by a microcomputer, the data is converted into a data of display form and written in a pattern memory and a color memory in the display memory 7. The data in the display memory 7 is read together with the processing operation and displayed on an EL display device 10 via an EL drive circuit 9.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention stores a part of a character signal sent in which information such as characters and graphics is superimposed on a part of the vertical blanking period of a television signal. This invention relates to a teletext receiver that outputs and displays the data on a display device after processing the data, and particularly improves the method of accessing the display memory.

<Prior Art> Generally, display memory (including buffer memory) needs to be accessible from both the software side and the hardware side. However, it is impossible to access from both at the same time, so one must be prioritized. Since the position of hardware access is determined by the display period and the multiplexing position of character signals, priority is usually given to hardware access.

It is well known that in the conventional method of accessing the display memory in a teletext receiver, when the display screen is accessed from the software side during the hardware read cycle period, characteristic noise appears on the display screen, resulting in an extremely unsightly screen. It is being Therefore, software processing consists of microcomputer-specific data processing (this refers to processing that does not access display memory and is called internal processing) as shown in Figure 1(b), and display processing as shown in Figure 1(c). It is divided into a software read/write cycle for the memory, and consideration has been given so that the software read/write cycle and the hardware read/write cycle do not overlap.

<Problems> However, with the conventional method described above, the processing capacity of the receiver is subject to time constraints due to the complexity of software processing and the inability to use software processing time effectively. was.

<Problem Solving Means> The present invention has been made in view of the above points, and uses an unnecessary time gap for the hardware to read the display memory from the software side even during the hardware read cycle period. The present invention provides a new access method that allows access to the computer and does not adversely affect the screen display.

<Examples> The present invention will be described below according to examples shown in the drawings. Second
The figure shows a block diagram of a teletext receiver according to the present invention, where 1 is an antenna, 2 is a tuner, 3 is a video detection circuit, 4 is a character extraction circuit, 5 is a synchronization separation circuit, and 6 is a 5-p
(serial-parallel) V) shift register, 7 is pattern memory, display memory including buffer memory in addition to color memory, 8fdP-5 (parallel-serial) V)
Shift register, 9uEL (electroluminescence) Ili1 circuit, 10 EL display device, 11 address switching circuit, 12 multi-gate control gate signal generation circuit, 13 hard address counter, 14 chip selector circuit, 15 set priority RS Flip-flop, 16 is a control ROM (IJ-DO71J-memory), 17 is a control RAM (random access memory),
18 is the CPU (central control unit), 19 is the keyboard, 20
21 is a memory write signal control circuit, and 21 is a display gate signal generation circuit.

” - In a teletext receiver consisting of the following,
The television signal on which the character signal has been superimposed is inputted through the antenna 1 and supplied to the tuner 2, where the desired television signal is selectively received, and this is supplied to the video detection circuit 3, where it is amplified by intermediate frequency and processed for video. After being detected,
The signal is supplied to a character extraction circuit 4 and a period separation circuit 5. The character extraction circuit 4 extracts only the character signal from the television video signal, converts this character signal into 8-bit parallel data through the S-P shift register 6, and writes it into the buffer memory in the display memory 7 ( The write operation is called a hardware write cycle). This display memory 7 includes an address switching circuit 1], a multiplexer control gate signal generation circuit 12, a hard address counter 13, a chip selector circuit 14, a set priority RS flip-flop 15, a CPU 1.8, and a memory write signal control circuit 20. Controls can be accessed from both software and hardware. ”-The character signal once taken into the buffer memory in the display memory 7 is stored in the control ROM 16 and the control R.
After being processed by the orange microcomputer from the AM, CPU 18 and keyboard 19, it is converted into display format data and written to the pattern memory and color memory in the display memory 7 (hereinafter, this write operation will be referred to as a software read/write cycle). ).

Simultaneously with the above processing operations, the display memory 7 is activated by a memory read circuit consisting of a P-S shift register 8, an address switching circuit 11, a multiplexer control gate signal generation circuit 12, a hard address counter 13, a display gate signal generation circuit 21, etc. The data within is sequentially read out and converted into displayable serial data (hereinafter, this read operation will be referred to as a hardware read cycle). The data thus obtained is displayed on the screen of the EL display device 10 via the EL drive circuit 9.

Next, a method of accessing the display memory 7, which is particularly relevant to the present invention, will be explained in detail using the time chart shown in FIG.

FIG. 3(a) shows a 5.73 MHz clock pulse for driving the S-P shift register 6, the P-S shift register 8, and the hard address counter 3.
It is used for read/write timing of the display memory 7 by hardware. During the hardware read cycle, the multiplexer control gate signal generating circuit 12 outputs a multiplex control zL/(MPXCNTL) signal as shown in FIG. 3(b), which is input to the address switching circuit 11. This signal is 5.73
Synchronized with MHz clock pulse, display memory 7
The purpose of this is to divide the address output period of the address at a ratio of 3 clocks for the hard address and 4 clocks for the soft address. As a result, the address bus of the display memory 7 is switched as shown in FIG. 3(d).
The signal P S LOAD shown in FIG. This indicates that data is read from the display memory 7. The signal Φ shown in FIG. 3(e) represents the clock pulse of the microcomputer, in particular CPU 1.8, where T1+72+73 represents the machine cycle, while Tw
indicates a WAIT cycle.

Now, suppose that the CPU 18 issues a request to access the display screen in the T+ cycle. At this time, the chip selector circuit 14 outputs a chip selector signal as shown in FIG. 3(f), which is the TI cycle. The display memory 7 which becomes active at the falling edge of is selected as a chip. The WAIT signal of the microcomputer shown in Figure 3 (g) becomes active and the CP
Issues a WAIT request to U18. Assume that the display memory 7 enters the hardware read mode as shown in the figure. At this time, the WAIT signal remains active and the microcomputer enters the T2 cycle. Then, the WAIT signal is detected at the falling edge of the T2 cycle, and the microcomputer enters the WAIT state.
Waiting for the IT signal to be released (8). The signal 100 shown in FIG. 3(c) is output on the eighth clock pulse, indicating the end of the hardware read period. At the falling edge of this signal, the third
The WAIT signal shown in Figure (g) is released, the microcomputer starts operating again, and a write operation on the software side is performed at the falling edge of T3. The WR multiplied signal shown in FIG. 3(h) is output from the falling edge of the T2 state to the falling edge of T (Nutate), and is output by the WAIT signal shown in FIG. 3(g) and the WR multiplied signal shown in FIG. 3(h). The memory write signal control circuit 20 outputs M- as shown in FIG. 3(i).
A WR multiplied signal is generated and supplied to the display memory 7 as a memory write signal.

<Effects> According to the present invention, as described above, it is a memory access method that utilizes the gap in the read period by hardware,
Only when hardware and software are accessed at the same time can a microcomputer be used as a hardware
Although the IT state is entered, the moment when the display memory is accessed in the microcomputer's instructions is very short, so the period during which the microcomputer is stopped is short, and extremely efficient processing operations are possible.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining a display memory access method in a conventional teletext receiver, FIG. 2 is a block diagram of a teletext receiver according to the present invention, and FIG. 3 is a block diagram of the teletext receiver according to the present invention. A time chart is shown when the access method is implemented. 4...Character sampling circuit, 7...Display memory, 10...
・EL display device. Agent Patent attorney Aihiko Fuku (and 2 others) Japanese Patent Application Publication No. 1973
9-154886 (5)

Claims (1)

[Claims] 1. In a teletext receiver that receives and displays a text multiplex signal in which information such as text and graphics is superimposed on part of the vertical blanking period of a television signal, the received text signal is transferred to the hardware. a means of manually importing the data into memory;
A microcomputer that processes the data captured in this memory using software, and a display memory that temporarily stores the processed data for display.
A teletext receiver comprising means for reading data in the display memory using hardware, and reading the data in the display memory using hardware and making the display memory accessible from the software side. How to access the display memory on the machine.