JPH083107Y2 - Magnetic recording / reproducing device with liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a magnetic recording / reproducing device with a liquid crystal display device.

(B) Prior Art A magnetic recording / reproducing device (VCR) having an integrated liquid crystal image display device is known (Japanese Patent Laid-Open No. 62-143578 H04N5 / 78).
3). FIG. 6 shows such a VCR with a liquid crystal display device.
In such a VCR, noise generated from the liquid crystal display device becomes a problem. That is, in the active matrix type liquid crystal display device, noise is generated when the liquid crystal display element is charged and discharged, and this noise is picked up by the head of the rotary cylinder 11 and put on the video signal.

(C) Problems to be Solved by the Invention Therefore, the present invention aims to prevent noise generated during charging and discharging of the liquid crystal display element from adversely affecting the video signal.

(D) Means for Solving the Problems In the present invention, a video signal delay means for delaying a video signal reproduced by a head for a predetermined time to create a delayed video signal, and a horizontal blanking signal included in the delayed video signal. Of a reset signal creating means for creating a reset signal having a predetermined pulse width from the start of, the charge and discharge control means for starting the discharge of the liquid crystal display element from the start of the reset signal and starting the charge from the end of the reset signal, Equipped with,
The predetermined pulse width of the reset signal is set to be equal to or shorter than the width of the horizontal blanking signal shortened for the predetermined time.

(E) Operation According to the above configuration, the noise is located outside the display period of the video signal, and the noise does not appear on the screen.

(F) Embodiment FIG. 1 shows the liquid crystal drive circuit 14 of the liquid crystal display panel 9 (the number of pixels m × n).
Driver 2 (number of terminals n), X driver 6 (number of terminals m),
It consists of a DC-AC converter 7 and a backlight 8. The Y drive bus 2 includes a shift register 3, a sample hold circuit 4,
It comprises an output buffer circuit 5.

The timing controller 1 outputs a start pulse and a shift clock to the X driver 6 and the Y driver 2, respectively, in synchronization with the horizontal and vertical blanking signals (Hs, Vs) of the video signal, the shift register 3 and the output buffer. The reset signal is output to the circuit 5.

The operation of the Y driver 2 is as follows. The start pulse input to the shift register 3 is shifted by the shift clock and is output from the shift register 3 as a sampling timing pulse. The sampling and holding circuit 4 samples the video signal and holds it in response to the sampling timing pulse. This sampling signal passes through the output buffer circuit 5 and is used as a Y drive signal in the corresponding liquid crystal display panel 9
Applied to the Y drive terminal of. The sampling and holding circuit 4 samples and holds a video signal of 1H and then outputs the Y drive signal of 1H at a time to the corresponding Y drive terminals in synchronization with the horizontal blanking signal.

Similarly, a start pulse is applied to the X driver 6,
In response to the shift clock, X drive signals are sequentially output to the X drive terminals of the liquid crystal display panel 9.

In this way, the video signal of 1H unit is applied to one line specified by the X drive signal at a time on the liquid crystal display panel 9 and displayed.

The reset signal is output from the timing controller 1 every 1H, and the shift register 3 and the output buffer circuit 5 are output.
And are reset to the initial state.

The liquid crystal display panel 9 is illuminated by the backlight 8 which is turned on by the output of the DC-AC converter 7.

Next, referring to FIGS. 2 and 3, one liquid crystal display device LCD
Then, how the video signal is written will be described.

The sample hold circuit 4 and the output buffer circuit 5 are
The number of pixels in one line, that is, n liquid crystal display elements LCD is provided. The sample hold circuit 4 is a capacitor C1,
It has C2 and switches S1, S2, S3 and S4. The output buffer circuit 5 has an amplifier 5a, a transistor 5b, and switches S5 and S6.

The two capacitors C1 and C2 of the sample and hold circuit 4 hold the video signals alternately sampled every 1H (see a, d and e in FIG. 3). That is, when the switch S1 is closed and the video signal is held in the capacitor C1 in a certain 1H, the switch S2 is closed and the 1H video signal is held in the next 1H.

When the sampling video signal is held in the capacitor C1 of the sample hold circuit 4 during a certain 1H period,
Reset signal output from the timing controller 1 in synchronization with the next horizontal blanking signal (see FIG. 3b)
Thereby, the switches S5 and S6 are closed (see FIG. 3h), the amplifier 5a is set to the initial state, and the electric charge held in the liquid crystal display element LCD is discharged (at this time, the transistor 9a is conductive and is discharged through the switch S5). When the reset signal falls to the low level and the switch S2 is closed, a new sampling signal is output through the output buffer circuit 5 and the transistor 9a to the liquid crystal display. Applied to the display element LCD.

The above operation is performed for all the liquid crystal display elements LCD for one line, and the sampling video signal for 1H is written at one time.

When writing of one line is completed, the drive output of the X driver 6 is shifted by one, and for the next one line, the video signal is held in the capacitor C2 of the sample hold circuit 4, and the same as above. A write operation is performed.

Now, when the switch S5 is operated to charge / discharge the liquid crystal display element LCD, noise is generated. This noise is picked up by the head 12 in the rotary cylinder 11 and is carried on the video signal. FIG. 5 shows such a relationship. The video signal picked up by the head 12 is applied to the video signal processing circuit 13 and subjected to processing such as demodulation and de-emphasis. The video signal thus processed is applied to the liquid crystal drive circuit 14. Further, horizontal and vertical blacking signals separated by the sync separation circuit 15 are also applied to the liquid crystal drive circuit 14. The liquid crystal display panel 9 is driven by the drive signal from the liquid crystal drive circuit 14.
The display timing of the liquid crystal display panel 9 is the liquid crystal drive circuit 14
It depends on the reset signal (this signal is synchronized with the horizontal blanking signal) output from the timing controller 1 therein. That is, as shown in FIG. 3, when the reset signal rises to the high level, the switches S5 and S6 are
Is closed and the liquid crystal display element LCD starts discharging. Then, when the reset signal falls, writing of a new video signal, that is, charging of the liquid crystal display element LCD is started. Noise is generated during this charging and discharging. By the way, in FIG. 5, between the point A and the circuit in the liquid crystal drive circuit 14,
There is a time delay of about 3.5 μSEC due to signal processing. Therefore, as shown in FIG. 4, in synchronization with the horizontal blanking signal in the liquid crystal drive circuit 14 (see FIG. 4b) which is delayed by about 3.5 μSEC from the horizontal blanking signal at point A (see FIG. 4a). When a reset signal is created (see FIG. 4c) and charging / discharging is performed in synchronization with the rising and falling of the reset signal, noise c1 due to discharging enters the horizontal blanking signal, but charging The resulting noise c2 enters the video signal period, and noise appears on the screen. Therefore, in the present invention, the width of the reset signal is shortened so that the noise d1 caused by the discharge is generated at the same position as the noise c1.
The noise d2 due to charging is configured to enter within the horizontal blanking period (excluding the burst signal portion). In reality, a video signal in the vicinity of the horizontal blanking period may not be displayed on the screen in some cases, and in this case, the video signal may slightly enter the video signal period. In short, it suffices that the noise caused by charging comes outside the display period. In this embodiment, the width of the reset signal is set to 7.0 μSEC. If this width is made too narrow, charging starts before the end of discharging, which causes a problem.

The width of the reset signal can be digitally created in the timing controller 1 based on the horizontal synchronizing signal, but may be processed by a circuit after being output from the timing controller 1.

(G) Effect of the Invention According to the present invention described above, it is possible to prevent noise generated during charging and discharging of the liquid crystal display element from appearing on the display screen.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the present invention, FIG. 2 is a diagram showing a sample hold circuit, an output buffer circuit and a liquid crystal display device, FIG. 3 is an operation waveform diagram, and FIG. 4 is a horizontal blanking signal, a reset signal and noise. 5 is a diagram showing the entire block of the magnetic recording / reproducing device, and FIG. 6 is an external view of the magnetic recording / reproducing device with a liquid crystal display device. 1 is a timing controller, 2 is a Y driver, 6 is an X driver, 9 is a liquid crystal display panel,

Claims (1)

[Scope of utility model registration request] 1. A head provided on a rotary cylinder, a liquid crystal display element for displaying a video signal reproduced by the head, and a video signal delay means for delaying the video signal for a predetermined time to create a delayed video signal. A reset signal generating means for generating a reset signal having a predetermined pulse width from the start of the horizontal blanking signal included in the delayed video signal; and starting discharge of the liquid crystal display element from the start of the reset signal, A charging / discharging control means for starting charging of the liquid crystal display element from the end of the reset signal, wherein the predetermined pulse width of the reset signal is shortened by the predetermined time of the width of the horizontal blanking signal. A magnetic recording / reproducing device with a liquid crystal display device, which is set to be equal to or shorter than the above.