JPS60128393U - Video memory control device - Google Patents

Video memory control device

Info

Publication number
JPS60128393U
JPS60128393U JP1521784U JP1521784U JPS60128393U JP S60128393 U JPS60128393 U JP S60128393U JP 1521784 U JP1521784 U JP 1521784U JP 1521784 U JP1521784 U JP 1521784U JP S60128393 U JPS60128393 U JP S60128393U
Authority
JP
Japan
Prior art keywords
video memory
register
horizontal
vertical
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1521784U
Other languages
Japanese (ja)
Inventor
清 岩井
鈴木 十士
Original Assignee
日本ボードコンピュータ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本ボードコンピュータ株式会社 filed Critical 日本ボードコンピュータ株式会社
Priority to JP1521784U priority Critical patent/JPS60128393U/en
Publication of JPS60128393U publication Critical patent/JPS60128393U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、パーソナルコンピュータよりCRTディスプ
レイに出力されている映像データ信号を本考案装置を介
して映像メモリへ記憶させる場合のブロック図である。 第2図は、本考案装置の構成の具体例を周辺装置との接
続において示すブロック図である。第3図は、CRT画
面の有効画面範囲とラスター範囲を示すCRT画面の正
面図である。第4図は、原画像の内から映像メモリへ記
憶させようとする画面部分を示す図である。第5図は、
垂直又は水平同期信号と映像輝度信号それぞれの波形図
である。
FIG. 1 is a block diagram when a video data signal output from a personal computer to a CRT display is stored in a video memory via the device of the present invention. FIG. 2 is a block diagram showing a specific example of the configuration of the device of the present invention in connection with peripheral devices. FIG. 3 is a front view of the CRT screen showing the effective screen range and raster range of the CRT screen. FIG. 4 is a diagram showing a screen portion of the original image to be stored in the video memory. Figure 5 shows
FIG. 3 is a waveform diagram of a vertical or horizontal synchronization signal and a video luminance signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 原画像の映像データ信号を入力し、データ処理を行なっ
たのち映像メモリへ記憶させる映像メモリ制御装置にお
いて、映像メモリへ記憶させようとする画像部分の始点
の垂直方向行数および水平方向素数をそれぞれ設定する
ための垂直方向座標レジスタ1および水平方向座標レジ
スタ2と、前記画像部分の垂直方向および水平方向の大
きさをそれぞれ設定するための垂直方向行数レジスタ3
および水平方向画素数レジスタ4と、前記各レジスタに
対応してそれぞれ設けられた垂直方向座標カウンタ1′
、水平方向座標ワウンタ2′、垂直方向行数カウンタ3
′、水平方向画素数カウンタ4′とを有し、原画像のデ
ータ入力信号から画素数および行数を前記各カウンタで
計数しながら、対応する前記各レジスタの設定値と比較
することにより、原画像の内から映像メモリへ記憶させ
ようとする画像部分の位置および大きさを規定した信号
を映像メモリに送出することを特徴とする映像メモリ制
御装置。
In a video memory control device that inputs the video data signal of the original image, performs data processing, and then stores it in the video memory, the number of vertical rows and the horizontal prime number of the starting point of the image part to be stored in the video memory are respectively determined. A vertical coordinate register 1 and a horizontal coordinate register 2 for setting, and a vertical line number register 3 for setting the vertical and horizontal sizes of the image portion, respectively.
and a horizontal pixel number register 4, and a vertical coordinate counter 1' provided corresponding to each register.
, horizontal coordinate counter 2', vertical line number counter 3
', a horizontal pixel number counter 4', and counts the number of pixels and rows from the data input signal of the original image with each of the counters, and compares it with the set value of each of the corresponding registers. A video memory control device characterized in that a signal defining the position and size of an image portion of an image to be stored in the video memory is sent to the video memory.
JP1521784U 1984-02-06 1984-02-06 Video memory control device Pending JPS60128393U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1521784U JPS60128393U (en) 1984-02-06 1984-02-06 Video memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1521784U JPS60128393U (en) 1984-02-06 1984-02-06 Video memory control device

Publications (1)

Publication Number Publication Date
JPS60128393U true JPS60128393U (en) 1985-08-28

Family

ID=30500860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1521784U Pending JPS60128393U (en) 1984-02-06 1984-02-06 Video memory control device

Country Status (1)

Country Link
JP (1) JPS60128393U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255386A (en) * 1985-05-09 1986-11-13 セイコーエプソン株式会社 Display unit
JPS63148782A (en) * 1986-12-11 1988-06-21 Fuji Kiki Kogyo Kk Video image recorder
JPH01155784A (en) * 1987-12-11 1989-06-19 Mitsubishi Electric Corp Video signal storing controller
JPH03196183A (en) * 1989-12-26 1991-08-27 Seiko Epson Corp Video processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5778087A (en) * 1980-10-31 1982-05-15 Tokyo Shibaura Electric Co Video information storage retrieving device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5778087A (en) * 1980-10-31 1982-05-15 Tokyo Shibaura Electric Co Video information storage retrieving device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255386A (en) * 1985-05-09 1986-11-13 セイコーエプソン株式会社 Display unit
JPS63148782A (en) * 1986-12-11 1988-06-21 Fuji Kiki Kogyo Kk Video image recorder
JPH01155784A (en) * 1987-12-11 1989-06-19 Mitsubishi Electric Corp Video signal storing controller
JPH03196183A (en) * 1989-12-26 1991-08-27 Seiko Epson Corp Video processor

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