JPH0319364A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve a semiconductor device of this design in electrostatic strength without increasing processes in number by a method wherein a cell of a memory part is provided with a first conductivity type substrate region and a second conductivity type first impurity region formed on the substrate region, and an input and an output section are made to have the same structure. CONSTITUTION:Conductor diffusion layers 105a and 106b whose impurity concentrations are different from that of a semiconductor substrate 101 of low concentration and diffusion layers 105a and 105b of high concentration are provided. An impurity layer 107 is formed in such a manner that its impurity is the same conductivity type with that of the substrate 101, and its impurity concentration increases slightly starting from, at least, the base of a diffusion layer between a source 106 and a drain 105 toward the surface side keeping a channel region or a part near the surface of the substrate unchanged in impurity concentration. An impurity region is provided under the diffusion layers 105 and 106 so as to improve a memory cell in stability to incident X rays. By this setup, an X-ray countermeasure is established and an impurity region 107 is formed under such a condition that a Snap back voltage is made to decrease.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in the structure of semiconductor devices. [Prior art] Figure 3(a) shows a conventional structure. In the figure, l is a semiconductor substrate, 2 is a gate insulator, 3 is a gate electrode, and 4 is a sidewall insulating film. 5a is a low concentration diffusion layer, and 5b is a high concentration diffusion layer. This is 5a
By arranging 5b on the outer side, it is possible to suppress the spread of impurities toward the channel side of the diffusion layer 5a and secure the channel length, and the invention is also applied to semiconductor devices that operate statically. [Problems to be Solved] In a semiconductor device having such a structure, the first part containing external input/output terminals, such as the output part, is shown in Fig. 3 (
In the output buffer transistor shown in b), particularly in the transistor in which 5a is made of P and 5b is made of As, a problem has occurred in that the electrostatic withstand voltage is low. The present invention aims to solve this problem. [Means for Solving the Problems] A semiconductor device of the present invention is characterized in that at least a part of the semiconductor device has a memory portion that performs static operation, in which a cell of the memory portion or a part of its periphery. The structure of the substrate is composed of a substrate region of a first conductivity type, a first impurity region of a second conductivity type formed on the substrate region, and a first conductivity type formed directly under the first impurity region, and This semiconductor device is characterized in that it includes a second impurity region with a high impurity concentration, and that part or all of the input and output portions have the same structure. [Example 1 Figure 1 shows an example of the present invention. In the figure, 10l is a semiconductor substrate, 102 is a gate insulating film, 103 is a gate electrode, 104 is a sidewall insulating film, I05a. l06a is a low concentration semiconductor substrate lO
105b and 106b are diffusion layers of a different conductor, 105 is a drain, and 106 is a source. Further, 107 is an impurity of the same conductivity type as the substrate 101, and the impurity concentration increases mainly at least from the low surface to the surface side of the diffusion layer between the source and drain, and does not change the impurity concentration in the channel region, that is, near the substrate surface. This is an impurity layer formed by this method. Now, the next document rThe Effect of Inte
rconnectProcess and Snapb
ack Voltage on the ESDFai
Lure Thrashield of NMOS Tr
ansistorJ IEEEETRANSACTION
ON ELEC RON DEVICE, VO
L35 No. 12DEC 1988, it has been found that the electrostatic withstand voltage depends on the pattern parameters of the transistor and the snap back voltage.
The k voltage is due to the operation of the N''-P-N'' parasitic bipolar transistor consisting of the source, train, and channel regions that constitute the Nch transistor. This Sn
In order to lower the ap-back voltage, it is necessary to shorten the effective channel length or increase the impurity concentration in the channel portion. However, it is difficult to shorten the effective channel length due to characteristic fluctuations due to bunch through and variations in gate length. Therefore, a method of increasing the impurity concentration in the channel part is used, but if the impurity concentration in the entire channel part is increased, vth will also change, so at least a region with high impurity concentration is placed deep below the substrate surface where it has little effect on vth. In other words, the first
All you need to do is form the image shown in Figure 107. Specifically, this can be achieved by high-voltage accelerated ion implantation. For example, if we take an Nch transistor as an example, the depth of the diffusion layer corresponding to 105 and 106 in Fig. 1 is 0.3.
When μ is ion implanted at 180 KeV'B''', the impurity layer 107 can be formed and the concentration peak is approximately 0.
．． At 48μ, the density can be adjusted by adjusting the amount of implantation. On the other hand, in order to form this impurity layer 107, one photolithography and one ion implantation are required, which increases the number of steps. However, in a semiconductor device that includes a memory that performs static operation, Buri is used to ensure the stability of the memory cell against the incidence of xB, as shown in Figure
A method has been adopted in which an impurity region 108 called "ed P" is provided under the diffusion layers 105 and 106. Therefore, in the present invention, the xi
The impurity region 108 is formed under conditions that lower the backiJ pressure.
By forming 107, both effects were achieved in one process. As described above, the structure of the present invention has been realized. [Effects of the invention] By using the structure of the present invention, the electrostatic withstand voltage could be improved without increasing the number of steps.

[Brief explanation of drawings]

Figures 1 and 2 are explanatory diagrams of the present invention, Figures 3 (a) and (b)
In FIG. 6, which is an explanatory diagram of the prior art, 1,101...semiconductor substrate 2,102...gate insulating film 3,103...gate electrode 4,104...side-all insulating film 5a... ... Diffusion layer region a with low concentration 5b ... High 1 05a ... Diffusion layer region 1 with low concentration of drain 05b ... High 1
06a... Diffusion layer region 1 with low source concentration 06b... 〃 High 〃 107.
...Region 108 with higher concentration than the substrate of the same conductivity type as the substrate = Buried P" or more

Claims (1)

[Claims] In a semiconductor device characterized in that at least a part of the semiconductor device has a memory portion that operates statically,
A substrate region in which a cell of the memory portion or a part of its surrounding structure is of a first conductivity type, a first impurity region of a second conductivity type formed on the substrate region, and directly below the first impurity region. The device is characterized by comprising a second impurity region of the first conductivity type formed in the substrate region and having a high impurity concentration in the substrate region, and in which some or all of the elements of the input and output portions have the same structure. semiconductor devices.